forked from Minki/linux
MIPS: Use GENERIC_IOMAP
MIPS has a copy of lib/iomap.c with minor alterations, none of which are
necessary given appropriate definitions of PIO_OFFSET, PIO_MASK &
PIO_RESERVED. Provide such definitions, select GENERIC_IOMAP & remove
arch/mips/lib/iomap.c to cut back on the needless duplication.
The one change this does make is to our mmio_{in,out}s[bwl] functions,
which began to deviate from their generic counterparts with commit
0845bb721e ("MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO"). I
suspect that this commit was incorrect, and that the SEAD-3 platform
should have instead selected CONFIG_SWAP_IO_SPACE. Since the SEAD-3
platform code is now gone & the board is instead supported by the
generic platform (CONFIG_MIPS_GENERIC) which selects
CONFIG_SWAP_IO_SPACE anyway, this shouldn't be a problem any more.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20342/
Cc: linux-mips@linux-mips.org
This commit is contained in:
Paul Burton
parent
e245767abf
commit
b962aeb022
@ -21,6 +21,7 @@ config MIPS
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select GENERIC_CLOCKEVENTS
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select GENERIC_CMOS_UPDATE
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select GENERIC_CPU_AUTOPROBE
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select GENERIC_IOMAP
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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select GENERIC_LIB_ASHLDI3
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@ -28,7 +29,6 @@ config MIPS
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select GENERIC_LIB_CMPDI2
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select GENERIC_LIB_LSHRDI3
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select GENERIC_LIB_UCMPDI2
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select GENERIC_PCI_IOMAP
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select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
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select GENERIC_SMP_IDLE_THREAD
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select GENERIC_TIME_VSYSCALL
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@ -79,6 +79,16 @@ static inline void set_io_port_base(unsigned long base)
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barrier();
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}
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/*
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* Provide the necessary definitions for generic iomap. We make use of
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* mips_io_port_base for iomap(), but we don't reserve any low addresses for
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* use with I/O ports.
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*/
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#define HAVE_ARCH_PIO_SIZE
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#define PIO_OFFSET mips_io_port_base
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#define PIO_MASK IO_SPACE_LIMIT
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#define PIO_RESERVED 0x0UL
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/*
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* Thanks to James van Artsdalen for a better timing-fix than
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* the two short jumps: using outb's to a nonexistent port seems
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@ -172,11 +182,6 @@ static inline void *isa_bus_to_virt(unsigned long address)
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extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
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extern void __iounmap(const volatile void __iomem *addr);
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#ifndef CONFIG_PCI
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struct pci_dev;
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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#endif
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static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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@ -7,7 +7,7 @@ lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \
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mips-atomic.o strncpy_user.o \
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strnlen_user.o uncached.o
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obj-y += iomap.o iomap_copy.o
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obj-y += iomap_copy.o
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obj-$(CONFIG_PCI) += iomap-pci.o
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lib-$(CONFIG_GENERIC_CSUM) := $(filter-out csum_partial.o, $(lib-y))
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@ -44,10 +44,3 @@ void __iomem *__pci_ioport_map(struct pci_dev *dev,
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}
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#endif /* CONFIG_PCI_DRIVERS_LEGACY */
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void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iounmap);
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@ -1,227 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Implement the default iomap interfaces
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*
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* (C) Copyright 2004 Linus Torvalds
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* (C) Copyright 2006 Ralf Baechle <ralf@linux-mips.org>
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* (C) Copyright 2007 MIPS Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/export.h>
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#include <asm/io.h>
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/*
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* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
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* access or a MMIO access, these functions don't care. The info is
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* encoded in the hardware mapping set up by the mapping functions
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* (or the cookie itself, depending on implementation and hw).
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*
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* The generic routines don't assume any hardware mappings, and just
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* encode the PIO/MMIO as part of the cookie. They coldly assume that
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* the MMIO IO mappings are not in the low address range.
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*
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* Architectures for which this is not true can't use this generic
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* implementation and should do their own copy.
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*/
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#define PIO_MASK 0x0ffffUL
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unsigned int ioread8(void __iomem *addr)
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{
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return readb(addr);
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}
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EXPORT_SYMBOL(ioread8);
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unsigned int ioread16(void __iomem *addr)
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{
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return readw(addr);
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}
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EXPORT_SYMBOL(ioread16);
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unsigned int ioread16be(void __iomem *addr)
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{
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return be16_to_cpu(__raw_readw(addr));
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}
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EXPORT_SYMBOL(ioread16be);
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unsigned int ioread32(void __iomem *addr)
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{
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return readl(addr);
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}
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EXPORT_SYMBOL(ioread32);
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unsigned int ioread32be(void __iomem *addr)
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{
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return be32_to_cpu(__raw_readl(addr));
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}
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EXPORT_SYMBOL(ioread32be);
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void iowrite8(u8 val, void __iomem *addr)
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{
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writeb(val, addr);
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}
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EXPORT_SYMBOL(iowrite8);
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void iowrite16(u16 val, void __iomem *addr)
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{
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writew(val, addr);
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}
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EXPORT_SYMBOL(iowrite16);
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void iowrite16be(u16 val, void __iomem *addr)
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{
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__raw_writew(cpu_to_be16(val), addr);
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}
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EXPORT_SYMBOL(iowrite16be);
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void iowrite32(u32 val, void __iomem *addr)
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{
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writel(val, addr);
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}
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EXPORT_SYMBOL(iowrite32);
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void iowrite32be(u32 val, void __iomem *addr)
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{
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__raw_writel(cpu_to_be32(val), addr);
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}
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EXPORT_SYMBOL(iowrite32be);
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/*
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* These are the "repeat MMIO read/write" functions.
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* Note the "__mem" accesses, since we want to convert
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* to CPU byte order if the host bus happens to not match the
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* endianness of PCI/ISA (see mach-generic/mangle-port.h).
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*/
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static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
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{
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while (--count >= 0) {
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u8 data = __mem_readb(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
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{
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while (--count >= 0) {
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u16 data = __mem_readw(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
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{
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while (--count >= 0) {
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u32 data = __mem_readl(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
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{
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while (--count >= 0) {
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__mem_writeb(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
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{
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while (--count >= 0) {
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__mem_writew(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
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{
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while (--count >= 0) {
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__mem_writel(*src, addr);
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src++;
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}
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}
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void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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mmio_insb(addr, dst, count);
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}
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EXPORT_SYMBOL(ioread8_rep);
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void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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mmio_insw(addr, dst, count);
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}
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EXPORT_SYMBOL(ioread16_rep);
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void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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mmio_insl(addr, dst, count);
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}
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EXPORT_SYMBOL(ioread32_rep);
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void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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mmio_outsb(addr, src, count);
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}
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EXPORT_SYMBOL(iowrite8_rep);
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void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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mmio_outsw(addr, src, count);
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}
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EXPORT_SYMBOL(iowrite16_rep);
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void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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mmio_outsl(addr, src, count);
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}
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EXPORT_SYMBOL(iowrite32_rep);
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/*
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* Create a virtual mapping cookie for an IO port range
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*
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* This uses the same mapping are as the in/out family which has to be setup
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* by the platform initialization code.
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*
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* Just to make matters somewhat more interesting on MIPS systems with
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* multiple host bridge each will have it's own ioport address space.
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*/
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static void __iomem *ioport_map_legacy(unsigned long port, unsigned int nr)
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{
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return (void __iomem *) (mips_io_port_base + port);
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}
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void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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if (port > PIO_MASK)
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return NULL;
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return ioport_map_legacy(port, nr);
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}
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EXPORT_SYMBOL(ioport_map);
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void ioport_unmap(void __iomem *addr)
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{
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/* Nothing to do */
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}
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EXPORT_SYMBOL(ioport_unmap);
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