forked from Minki/linux
Thumb-2: Implementation of the unified start-up and exceptions code
This patch implements the ARM/Thumb-2 unified kernel start-up and exception handling code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas
parent
0becb08850
commit
b86040a59f
@ -127,3 +127,14 @@
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#endif
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#endif
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.endm
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#ifdef CONFIG_THUMB2_KERNEL
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.macro setmode, mode, reg
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mov \reg, #\mode
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msr cpsr_c, \reg
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.endm
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#else
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.macro setmode, mode, reg
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msr cpsr_c, #\mode
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.endm
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#endif
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@ -99,6 +99,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
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__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
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"1: ldrt %0, [%3]\n"
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" teq %0, %1\n"
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" it eq @ explicit IT needed for the 2b label\n"
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"2: streqt %2, [%3]\n"
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"3:\n"
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" .section __ex_table,\"a\"\n"
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@ -34,7 +34,7 @@
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@
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@ routine called with r0 = irq number, r1 = struct pt_regs *
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@
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adrne lr, 1b
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adrne lr, BSYM(1b)
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bne asm_do_IRQ
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#ifdef CONFIG_SMP
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@ -46,13 +46,13 @@
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*/
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test_for_ipi r0, r6, r5, lr
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movne r0, sp
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adrne lr, 1b
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adrne lr, BSYM(1b)
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bne do_IPI
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#ifdef CONFIG_LOCAL_TIMERS
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test_for_ltirq r0, r6, r5, lr
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movne r0, sp
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adrne lr, 1b
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adrne lr, BSYM(1b)
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bne do_local_timer
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#endif
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#endif
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@ -70,7 +70,10 @@
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*/
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.macro inv_entry, reason
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sub sp, sp, #S_FRAME_SIZE
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stmib sp, {r1 - lr}
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ARM( stmib sp, {r1 - lr} )
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THUMB( stmia sp, {r0 - r12} )
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THUMB( str sp, [sp, #S_SP] )
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THUMB( str lr, [sp, #S_LR] )
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mov r1, #\reason
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.endm
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@ -126,17 +129,24 @@ ENDPROC(__und_invalid)
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.macro svc_entry, stack_hole=0
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UNWIND(.fnstart )
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UNWIND(.save {r0 - pc} )
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sub sp, sp, #(S_FRAME_SIZE + \stack_hole)
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sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
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#ifdef CONFIG_THUMB2_KERNEL
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SPFIX( str r0, [sp] ) @ temporarily saved
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SPFIX( mov r0, sp )
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SPFIX( tst r0, #4 ) @ test original stack alignment
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SPFIX( ldr r0, [sp] ) @ restored
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#else
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SPFIX( tst sp, #4 )
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SPFIX( bicne sp, sp, #4 )
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stmib sp, {r1 - r12}
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#endif
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SPFIX( subeq sp, sp, #4 )
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stmia sp, {r1 - r12}
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ldmia r0, {r1 - r3}
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add r5, sp, #S_SP @ here for interlock avoidance
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add r5, sp, #S_SP - 4 @ here for interlock avoidance
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mov r4, #-1 @ "" "" "" ""
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add r0, sp, #(S_FRAME_SIZE + \stack_hole)
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SPFIX( addne r0, r0, #4 )
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str r1, [sp] @ save the "real" r0 copied
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add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
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SPFIX( addeq r0, r0, #4 )
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str r1, [sp, #-4]! @ save the "real" r0 copied
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@ from the exception stack
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mov r1, lr
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@ -196,9 +206,8 @@ __dabt_svc:
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@
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@ restore SPSR and restart the instruction
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@
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ldr r0, [sp, #S_PSR]
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msr spsr_cxsf, r0
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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ldr r2, [sp, #S_PSR]
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svc_exit r2 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__dabt_svc)
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@ -225,13 +234,12 @@ __irq_svc:
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tst r0, #_TIF_NEED_RESCHED
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blne svc_preempt
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#endif
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ldr r0, [sp, #S_PSR] @ irqs are already disabled
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msr spsr_cxsf, r0
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ldr r4, [sp, #S_PSR] @ irqs are already disabled
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#ifdef CONFIG_TRACE_IRQFLAGS
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tst r0, #PSR_I_BIT
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tst r4, #PSR_I_BIT
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bleq trace_hardirqs_on
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#endif
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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svc_exit r4 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__irq_svc)
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@ -266,7 +274,7 @@ __und_svc:
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@ r0 - instruction
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@
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ldr r0, [r2, #-4]
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adr r9, 1f
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adr r9, BSYM(1f)
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bl call_fpe
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mov r0, sp @ struct pt_regs *regs
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@ -280,9 +288,8 @@ __und_svc:
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@
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@ restore SPSR and restart the instruction
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@
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ldr lr, [sp, #S_PSR] @ Get SVC cpsr
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msr spsr_cxsf, lr
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ldmia sp, {r0 - pc}^ @ Restore SVC registers
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ldr r2, [sp, #S_PSR] @ Get SVC cpsr
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svc_exit r2 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__und_svc)
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@ -323,9 +330,8 @@ __pabt_svc:
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@
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@ restore SPSR and restart the instruction
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@
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ldr r0, [sp, #S_PSR]
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msr spsr_cxsf, r0
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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ldr r2, [sp, #S_PSR]
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svc_exit r2 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__pabt_svc)
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@ -353,7 +359,8 @@ ENDPROC(__pabt_svc)
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UNWIND(.fnstart )
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UNWIND(.cantunwind ) @ don't unwind the user space
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sub sp, sp, #S_FRAME_SIZE
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stmib sp, {r1 - r12}
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ARM( stmib sp, {r1 - r12} )
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THUMB( stmia sp, {r0 - r12} )
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ldmia r0, {r1 - r3}
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add r0, sp, #S_PC @ here for interlock avoidance
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@ -372,7 +379,8 @@ ENDPROC(__pabt_svc)
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@ Also, separately save sp_usr and lr_usr
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@
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stmia r0, {r2 - r4}
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stmdb r0, {sp, lr}^
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ARM( stmdb r0, {sp, lr}^ )
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THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
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@
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@ Enable the alignment trap while in kernel mode
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@ -427,7 +435,7 @@ __dabt_usr:
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@
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enable_irq
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mov r2, sp
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adr lr, ret_from_exception
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adr lr, BSYM(ret_from_exception)
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b do_DataAbort
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UNWIND(.fnend )
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ENDPROC(__dabt_usr)
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@ -452,7 +460,9 @@ __irq_usr:
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ldr r0, [tsk, #TI_PREEMPT]
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str r8, [tsk, #TI_PREEMPT]
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teq r0, r7
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strne r0, [r0, -r0]
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ARM( strne r0, [r0, -r0] )
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THUMB( movne r0, #0 )
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THUMB( strne r0, [r0] )
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#endif
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_on
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@ -476,9 +486,10 @@ __und_usr:
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@
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@ r0 - instruction
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@
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adr r9, ret_from_exception
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adr lr, __und_usr_unknown
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adr r9, BSYM(ret_from_exception)
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adr lr, BSYM(__und_usr_unknown)
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tst r3, #PSR_T_BIT @ Thumb mode?
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itet eq @ explicit IT needed for the 1f label
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subeq r4, r2, #4 @ ARM instr at LR - 4
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subne r4, r2, #2 @ Thumb instr at LR - 2
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1: ldreqt r0, [r4]
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@ -488,7 +499,10 @@ __und_usr:
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beq call_fpe
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@ Thumb instruction
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#if __LINUX_ARM_ARCH__ >= 7
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2: ldrht r5, [r4], #2
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2:
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ARM( ldrht r5, [r4], #2 )
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THUMB( ldrht r5, [r4] )
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THUMB( add r4, r4, #2 )
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and r0, r5, #0xf800 @ mask bits 111x x... .... ....
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cmp r0, #0xe800 @ 32bit instruction if xx != 0
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blo __und_usr_unknown
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@ -577,9 +591,11 @@ call_fpe:
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moveq pc, lr
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get_thread_info r10 @ get current thread
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and r8, r0, #0x00000f00 @ mask out CP number
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THUMB( lsr r8, r8, #8 )
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mov r7, #1
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add r6, r10, #TI_USED_CP
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strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
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ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
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THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
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#ifdef CONFIG_IWMMXT
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@ Test if we need to give access to iWMMXt coprocessors
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ldr r5, [r10, #TI_FLAGS]
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@ -587,36 +603,38 @@ call_fpe:
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movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
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bcs iwmmxt_task_enable
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#endif
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add pc, pc, r8, lsr #6
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mov r0, r0
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ARM( add pc, pc, r8, lsr #6 )
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THUMB( lsl r8, r8, #2 )
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THUMB( add pc, r8 )
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nop
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mov pc, lr @ CP#0
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b do_fpe @ CP#1 (FPE)
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b do_fpe @ CP#2 (FPE)
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mov pc, lr @ CP#3
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W(mov) pc, lr @ CP#0
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W(b) do_fpe @ CP#1 (FPE)
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W(b) do_fpe @ CP#2 (FPE)
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W(mov) pc, lr @ CP#3
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#ifdef CONFIG_CRUNCH
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b crunch_task_enable @ CP#4 (MaverickCrunch)
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b crunch_task_enable @ CP#5 (MaverickCrunch)
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b crunch_task_enable @ CP#6 (MaverickCrunch)
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#else
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mov pc, lr @ CP#4
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mov pc, lr @ CP#5
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mov pc, lr @ CP#6
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W(mov) pc, lr @ CP#4
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W(mov) pc, lr @ CP#5
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W(mov) pc, lr @ CP#6
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#endif
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mov pc, lr @ CP#7
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mov pc, lr @ CP#8
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mov pc, lr @ CP#9
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W(mov) pc, lr @ CP#7
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W(mov) pc, lr @ CP#8
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W(mov) pc, lr @ CP#9
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#ifdef CONFIG_VFP
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b do_vfp @ CP#10 (VFP)
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b do_vfp @ CP#11 (VFP)
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W(b) do_vfp @ CP#10 (VFP)
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W(b) do_vfp @ CP#11 (VFP)
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#else
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mov pc, lr @ CP#10 (VFP)
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mov pc, lr @ CP#11 (VFP)
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W(mov) pc, lr @ CP#10 (VFP)
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W(mov) pc, lr @ CP#11 (VFP)
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#endif
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mov pc, lr @ CP#12
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mov pc, lr @ CP#13
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mov pc, lr @ CP#14 (Debug)
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mov pc, lr @ CP#15 (Control)
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W(mov) pc, lr @ CP#12
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W(mov) pc, lr @ CP#13
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W(mov) pc, lr @ CP#14 (Debug)
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W(mov) pc, lr @ CP#15 (Control)
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#ifdef CONFIG_NEON
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.align 6
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@ -667,7 +685,7 @@ no_fp: mov pc, lr
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__und_usr_unknown:
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enable_irq
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mov r0, sp
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adr lr, ret_from_exception
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adr lr, BSYM(ret_from_exception)
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b do_undefinstr
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ENDPROC(__und_usr_unknown)
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@ -711,7 +729,10 @@ ENTRY(__switch_to)
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UNWIND(.cantunwind )
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add ip, r1, #TI_CPU_SAVE
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ldr r3, [r2, #TI_TP_VALUE]
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stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
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ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
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THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
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THUMB( str sp, [ip], #4 )
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THUMB( str lr, [ip], #4 )
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#ifdef CONFIG_MMU
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ldr r6, [r2, #TI_CPU_DOMAIN]
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#endif
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@ -736,8 +757,12 @@ ENTRY(__switch_to)
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ldr r0, =thread_notify_head
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mov r1, #THREAD_NOTIFY_SWITCH
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bl atomic_notifier_call_chain
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THUMB( mov ip, r4 )
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mov r0, r5
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ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
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ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
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THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
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THUMB( ldr sp, [ip], #4 )
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THUMB( ldr pc, [ip] )
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UNWIND(.fnend )
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ENDPROC(__switch_to)
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@ -772,6 +797,7 @@ ENDPROC(__switch_to)
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* if your compiled code is not going to use the new instructions for other
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* purpose.
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*/
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THUMB( .arm )
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.macro usr_ret, reg
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#ifdef CONFIG_ARM_THUMB
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@ -1020,6 +1046,7 @@ __kuser_helper_version: @ 0xffff0ffc
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.globl __kuser_helper_end
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__kuser_helper_end:
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THUMB( .thumb )
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/*
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* Vector stubs.
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@ -1054,15 +1081,17 @@ vector_\name:
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@ Prepare for SVC32 mode. IRQs remain disabled.
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@
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mrs r0, cpsr
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eor r0, r0, #(\mode ^ SVC_MODE)
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eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
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msr spsr_cxsf, r0
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@
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@ the branch table must immediately follow this code
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@
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and lr, lr, #0x0f
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THUMB( adr r0, 1f )
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THUMB( ldr lr, [r0, lr, lsl #2] )
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mov r0, sp
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ldr lr, [pc, lr, lsl #2]
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ARM( ldr lr, [pc, lr, lsl #2] )
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movs pc, lr @ branch to handler in SVC mode
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ENDPROC(vector_\name)
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@ -1206,14 +1235,16 @@ __stubs_end:
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.globl __vectors_start
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__vectors_start:
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swi SYS_ERROR0
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b vector_und + stubs_offset
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ldr pc, .LCvswi + stubs_offset
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b vector_pabt + stubs_offset
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b vector_dabt + stubs_offset
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b vector_addrexcptn + stubs_offset
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b vector_irq + stubs_offset
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b vector_fiq + stubs_offset
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ARM( swi SYS_ERROR0 )
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THUMB( svc #0 )
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THUMB( nop )
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W(b) vector_und + stubs_offset
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W(ldr) pc, .LCvswi + stubs_offset
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W(b) vector_pabt + stubs_offset
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W(b) vector_dabt + stubs_offset
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W(b) vector_addrexcptn + stubs_offset
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W(b) vector_irq + stubs_offset
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W(b) vector_fiq + stubs_offset
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.globl __vectors_end
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__vectors_end:
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@ -33,14 +33,7 @@ ret_fast_syscall:
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/* perform architecture specific actions before user return */
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arch_ret_to_user r1, lr
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@ fast_restore_user_regs
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ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr
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ldr lr, [sp, #S_OFF + S_PC]! @ get pc
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msr spsr_cxsf, r1 @ save in spsr_svc
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ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
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mov r0, r0
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add sp, sp, #S_FRAME_SIZE - S_PC
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movs pc, lr @ return & move spsr_svc into cpsr
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restore_user_regs fast = 1, offset = S_OFF
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UNWIND(.fnend )
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/*
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@ -73,14 +66,7 @@ no_work_pending:
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/* perform architecture specific actions before user return */
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arch_ret_to_user r1, lr
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@ slow_restore_user_regs
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ldr r1, [sp, #S_PSR] @ get calling cpsr
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ldr lr, [sp, #S_PC]! @ get pc
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msr spsr_cxsf, r1 @ save in spsr_svc
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ldmdb sp, {r0 - lr}^ @ get calling r0 - lr
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mov r0, r0
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add sp, sp, #S_FRAME_SIZE - S_PC
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movs pc, lr @ return & move spsr_svc into cpsr
|
||||
restore_user_regs fast = 0, offset = 0
|
||||
ENDPROC(ret_to_user)
|
||||
|
||||
/*
|
||||
@ -182,8 +168,10 @@ ftrace_stub:
|
||||
ENTRY(vector_swi)
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Calling r0 - r12
|
||||
add r8, sp, #S_PC
|
||||
stmdb r8, {sp, lr}^ @ Calling sp, lr
|
||||
ARM( add r8, sp, #S_PC )
|
||||
ARM( stmdb r8, {sp, lr}^ ) @ Calling sp, lr
|
||||
THUMB( mov r8, sp )
|
||||
THUMB( store_user_sp_lr r8, r10, S_SP ) @ calling sp, lr
|
||||
mrs r8, spsr @ called from non-FIQ mode, so ok.
|
||||
str lr, [sp, #S_PC] @ Save calling PC
|
||||
str r8, [sp, #S_PSR] @ Save CPSR
|
||||
@ -272,7 +260,7 @@ ENTRY(vector_swi)
|
||||
bne __sys_trace
|
||||
|
||||
cmp scno, #NR_syscalls @ check upper syscall limit
|
||||
adr lr, ret_fast_syscall @ return address
|
||||
adr lr, BSYM(ret_fast_syscall) @ return address
|
||||
ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
|
||||
|
||||
add r1, sp, #S_OFF
|
||||
@ -293,7 +281,7 @@ __sys_trace:
|
||||
mov r0, #0 @ trace entry [IP = 0]
|
||||
bl syscall_trace
|
||||
|
||||
adr lr, __sys_trace_return @ return address
|
||||
adr lr, BSYM(__sys_trace_return) @ return address
|
||||
mov scno, r0 @ syscall number (possibly new)
|
||||
add r1, sp, #S_R0 + S_OFF @ pointer to regs
|
||||
cmp scno, #NR_syscalls @ check upper syscall limit
|
||||
|
||||
@ -36,11 +36,6 @@
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro get_thread_info, rd
|
||||
mov \rd, sp, lsr #13
|
||||
mov \rd, \rd, lsl #13
|
||||
.endm
|
||||
|
||||
.macro alignment_trap, rtemp
|
||||
#ifdef CONFIG_ALIGNMENT_TRAP
|
||||
ldr \rtemp, .LCcralign
|
||||
@ -49,6 +44,93 @@
|
||||
#endif
|
||||
.endm
|
||||
|
||||
@
|
||||
@ Store/load the USER SP and LR registers by switching to the SYS
|
||||
@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
|
||||
@ available. Should only be called from SVC mode
|
||||
@
|
||||
.macro store_user_sp_lr, rd, rtemp, offset = 0
|
||||
mrs \rtemp, cpsr
|
||||
eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
|
||||
msr cpsr_c, \rtemp @ switch to the SYS mode
|
||||
|
||||
str sp, [\rd, #\offset] @ save sp_usr
|
||||
str lr, [\rd, #\offset + 4] @ save lr_usr
|
||||
|
||||
eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
|
||||
msr cpsr_c, \rtemp @ switch back to the SVC mode
|
||||
.endm
|
||||
|
||||
.macro load_user_sp_lr, rd, rtemp, offset = 0
|
||||
mrs \rtemp, cpsr
|
||||
eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
|
||||
msr cpsr_c, \rtemp @ switch to the SYS mode
|
||||
|
||||
ldr sp, [\rd, #\offset] @ load sp_usr
|
||||
ldr lr, [\rd, #\offset + 4] @ load lr_usr
|
||||
|
||||
eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
|
||||
msr cpsr_c, \rtemp @ switch back to the SVC mode
|
||||
.endm
|
||||
|
||||
#ifndef CONFIG_THUMB2_KERNEL
|
||||
.macro svc_exit, rpsr
|
||||
msr spsr_cxsf, \rpsr
|
||||
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
||||
.endm
|
||||
|
||||
.macro restore_user_regs, fast = 0, offset = 0
|
||||
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [sp, #\offset + S_PC]! @ get pc
|
||||
msr spsr_cxsf, r1 @ save in spsr_svc
|
||||
.if \fast
|
||||
ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
|
||||
.else
|
||||
ldmdb sp, {r0 - lr}^ @ get calling r0 - lr
|
||||
.endif
|
||||
add sp, sp, #S_FRAME_SIZE - S_PC
|
||||
movs pc, lr @ return & move spsr_svc into cpsr
|
||||
.endm
|
||||
|
||||
.macro get_thread_info, rd
|
||||
mov \rd, sp, lsr #13
|
||||
mov \rd, \rd, lsl #13
|
||||
.endm
|
||||
#else /* CONFIG_THUMB2_KERNEL */
|
||||
.macro svc_exit, rpsr
|
||||
ldr r0, [sp, #S_SP] @ top of the stack
|
||||
ldr r1, [sp, #S_PC] @ return address
|
||||
tst r0, #4 @ orig stack 8-byte aligned?
|
||||
stmdb r0, {r1, \rpsr} @ rfe context
|
||||
ldmia sp, {r0 - r12}
|
||||
ldr lr, [sp, #S_LR]
|
||||
addeq sp, sp, #S_FRAME_SIZE - 8 @ aligned
|
||||
addne sp, sp, #S_FRAME_SIZE - 4 @ not aligned
|
||||
rfeia sp!
|
||||
.endm
|
||||
|
||||
.macro restore_user_regs, fast = 0, offset = 0
|
||||
mov r2, sp
|
||||
load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
|
||||
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [sp, #\offset + S_PC] @ get pc
|
||||
add sp, sp, #\offset + S_SP
|
||||
msr spsr_cxsf, r1 @ save in spsr_svc
|
||||
.if \fast
|
||||
ldmdb sp, {r1 - r12} @ get calling r1 - r12
|
||||
.else
|
||||
ldmdb sp, {r0 - r12} @ get calling r0 - r12
|
||||
.endif
|
||||
add sp, sp, #S_FRAME_SIZE - S_SP
|
||||
movs pc, lr @ return & move spsr_svc into cpsr
|
||||
.endm
|
||||
|
||||
.macro get_thread_info, rd
|
||||
mov \rd, sp
|
||||
lsr \rd, \rd, #13
|
||||
mov \rd, \rd, lsl #13
|
||||
.endm
|
||||
#endif /* !CONFIG_THUMB2_KERNEL */
|
||||
|
||||
/*
|
||||
* These are the registers used in the syscall handler, and allow us to
|
||||
|
||||
@ -52,7 +52,9 @@ __mmap_switched:
|
||||
strcc fp, [r6],#4
|
||||
bcc 1b
|
||||
|
||||
ldmia r3, {r4, r5, r6, r7, sp}
|
||||
ARM( ldmia r3, {r4, r5, r6, r7, sp})
|
||||
THUMB( ldmia r3, {r4, r5, r6, r7} )
|
||||
THUMB( ldr sp, [r3, #16] )
|
||||
str r9, [r4] @ Save processor ID
|
||||
str r1, [r5] @ Save machine type
|
||||
str r2, [r6] @ Save atags pointer
|
||||
@ -156,7 +158,8 @@ ENDPROC(__error)
|
||||
*/
|
||||
__lookup_processor_type:
|
||||
adr r3, 3f
|
||||
ldmda r3, {r5 - r7}
|
||||
ldmia r3, {r5 - r7}
|
||||
add r3, r3, #8
|
||||
sub r3, r3, r7 @ get offset between virt&phys
|
||||
add r5, r5, r3 @ convert virt addresses to
|
||||
add r6, r6, r3 @ physical address space
|
||||
@ -187,9 +190,9 @@ ENDPROC(lookup_processor_type)
|
||||
* more information about the __proc_info and __arch_info structures.
|
||||
*/
|
||||
.align 2
|
||||
.long __proc_info_begin
|
||||
3: .long __proc_info_begin
|
||||
.long __proc_info_end
|
||||
3: .long .
|
||||
4: .long .
|
||||
.long __arch_info_begin
|
||||
.long __arch_info_end
|
||||
|
||||
@ -205,7 +208,7 @@ ENDPROC(lookup_processor_type)
|
||||
* r5 = mach_info pointer in physical address space
|
||||
*/
|
||||
__lookup_machine_type:
|
||||
adr r3, 3b
|
||||
adr r3, 4b
|
||||
ldmia r3, {r4, r5, r6}
|
||||
sub r3, r3, r4 @ get offset between virt&phys
|
||||
add r5, r5, r3 @ convert virt addresses to
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
*/
|
||||
.section ".text.head", "ax"
|
||||
ENTRY(stext)
|
||||
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
|
||||
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
|
||||
@ and irqs disabled
|
||||
#ifndef CONFIG_CPU_CP15
|
||||
ldr r9, =CONFIG_PROCESSOR_ID
|
||||
@ -50,8 +50,10 @@ ENTRY(stext)
|
||||
|
||||
ldr r13, __switch_data @ address to jump to after
|
||||
@ the initialization is done
|
||||
adr lr, __after_proc_init @ return (PIC) address
|
||||
add pc, r10, #PROCINFO_INITFUNC
|
||||
adr lr, BSYM(__after_proc_init) @ return (PIC) address
|
||||
ARM( add pc, r10, #PROCINFO_INITFUNC )
|
||||
THUMB( add r12, r10, #PROCINFO_INITFUNC )
|
||||
THUMB( mov pc, r12 )
|
||||
ENDPROC(stext)
|
||||
|
||||
/*
|
||||
@ -82,7 +84,8 @@ __after_proc_init:
|
||||
mcr p15, 0, r0, c1, c0, 0 @ write control reg
|
||||
#endif /* CONFIG_CPU_CP15 */
|
||||
|
||||
mov pc, r13 @ clear the BSS and jump
|
||||
mov r3, r13
|
||||
mov pc, r3 @ clear the BSS and jump
|
||||
@ to start_kernel
|
||||
ENDPROC(__after_proc_init)
|
||||
.ltorg
|
||||
|
||||
@ -76,7 +76,7 @@
|
||||
*/
|
||||
.section ".text.head", "ax"
|
||||
ENTRY(stext)
|
||||
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
|
||||
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
|
||||
@ and irqs disabled
|
||||
mrc p15, 0, r9, c0, c0 @ get processor id
|
||||
bl __lookup_processor_type @ r5=procinfo r9=cpuid
|
||||
@ -97,8 +97,10 @@ ENTRY(stext)
|
||||
*/
|
||||
ldr r13, __switch_data @ address to jump to after
|
||||
@ mmu has been enabled
|
||||
adr lr, __enable_mmu @ return (PIC) address
|
||||
add pc, r10, #PROCINFO_INITFUNC
|
||||
adr lr, BSYM(__enable_mmu) @ return (PIC) address
|
||||
ARM( add pc, r10, #PROCINFO_INITFUNC )
|
||||
THUMB( add r12, r10, #PROCINFO_INITFUNC )
|
||||
THUMB( mov pc, r12 )
|
||||
ENDPROC(stext)
|
||||
|
||||
#if defined(CONFIG_SMP)
|
||||
@ -110,7 +112,7 @@ ENTRY(secondary_startup)
|
||||
* the processor type - there is no need to check the machine type
|
||||
* as it has already been validated by the primary processor.
|
||||
*/
|
||||
msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
|
||||
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
|
||||
mrc p15, 0, r9, c0, c0 @ get processor id
|
||||
bl __lookup_processor_type
|
||||
movs r10, r5 @ invalid processor?
|
||||
@ -121,12 +123,15 @@ ENTRY(secondary_startup)
|
||||
* Use the page tables supplied from __cpu_up.
|
||||
*/
|
||||
adr r4, __secondary_data
|
||||
ldmia r4, {r5, r7, r13} @ address to jump to after
|
||||
ldmia r4, {r5, r7, r12} @ address to jump to after
|
||||
sub r4, r4, r5 @ mmu has been enabled
|
||||
ldr r4, [r7, r4] @ get secondary_data.pgdir
|
||||
adr lr, __enable_mmu @ return address
|
||||
add pc, r10, #PROCINFO_INITFUNC @ initialise processor
|
||||
@ (return control reg)
|
||||
adr lr, BSYM(__enable_mmu) @ return address
|
||||
mov r13, r12 @ __secondary_switched address
|
||||
ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
|
||||
@ (return control reg)
|
||||
THUMB( add r12, r10, #PROCINFO_INITFUNC )
|
||||
THUMB( mov pc, r12 )
|
||||
ENDPROC(secondary_startup)
|
||||
|
||||
/*
|
||||
@ -193,8 +198,8 @@ __turn_mmu_on:
|
||||
mcr p15, 0, r0, c1, c0, 0 @ write control reg
|
||||
mrc p15, 0, r3, c0, c0, 0 @ read id reg
|
||||
mov r3, r3
|
||||
mov r3, r3
|
||||
mov pc, r13
|
||||
mov r3, r13
|
||||
mov pc, r3
|
||||
ENDPROC(__turn_mmu_on)
|
||||
|
||||
|
||||
@ -235,7 +240,8 @@ __create_page_tables:
|
||||
* will be removed by paging_init(). We use our current program
|
||||
* counter to determine corresponding section base address.
|
||||
*/
|
||||
mov r6, pc, lsr #20 @ start of kernel section
|
||||
mov r6, pc
|
||||
mov r6, r6, lsr #20 @ start of kernel section
|
||||
orr r3, r7, r6, lsl #20 @ flags + kernel base
|
||||
str r3, [r4, r6, lsl #2] @ identity mapping
|
||||
|
||||
|
||||
@ -388,7 +388,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
|
||||
regs.ARM_r2 = (unsigned long)fn;
|
||||
regs.ARM_r3 = (unsigned long)kernel_thread_exit;
|
||||
regs.ARM_pc = (unsigned long)kernel_thread_helper;
|
||||
regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
|
||||
regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
|
||||
|
||||
return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
|
||||
}
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#include <linux/smp.h>
|
||||
#include <linux/fs.h>
|
||||
|
||||
#include <asm/unified.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/elf.h>
|
||||
@ -326,26 +327,39 @@ void cpu_init(void)
|
||||
BUG();
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the placement constraint for the inline asm directive below.
|
||||
* In Thumb-2, msr with an immediate value is not allowed.
|
||||
*/
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
#define PLC "r"
|
||||
#else
|
||||
#define PLC "I"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* setup stacks for re-entrant exception handlers
|
||||
*/
|
||||
__asm__ (
|
||||
"msr cpsr_c, %1\n\t"
|
||||
"add sp, %0, %2\n\t"
|
||||
"add r14, %0, %2\n\t"
|
||||
"mov sp, r14\n\t"
|
||||
"msr cpsr_c, %3\n\t"
|
||||
"add sp, %0, %4\n\t"
|
||||
"add r14, %0, %4\n\t"
|
||||
"mov sp, r14\n\t"
|
||||
"msr cpsr_c, %5\n\t"
|
||||
"add sp, %0, %6\n\t"
|
||||
"add r14, %0, %6\n\t"
|
||||
"mov sp, r14\n\t"
|
||||
"msr cpsr_c, %7"
|
||||
:
|
||||
: "r" (stk),
|
||||
"I" (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
|
||||
PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
|
||||
"I" (offsetof(struct stack, irq[0])),
|
||||
"I" (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
|
||||
PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
|
||||
"I" (offsetof(struct stack, abt[0])),
|
||||
"I" (PSR_F_BIT | PSR_I_BIT | UND_MODE),
|
||||
PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
|
||||
"I" (offsetof(struct stack, und[0])),
|
||||
"I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
|
||||
PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
|
||||
: "r14");
|
||||
}
|
||||
|
||||
|
||||
@ -62,7 +62,11 @@ struct unwind_ctrl_block {
|
||||
};
|
||||
|
||||
enum regs {
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
FP = 7,
|
||||
#else
|
||||
FP = 11,
|
||||
#endif
|
||||
SP = 13,
|
||||
LR = 14,
|
||||
PC = 15
|
||||
|
||||
Loading…
Reference in New Issue
Block a user