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ARM: make cr_alignment read-only #ifndef CONFIG_CPU_CP15

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This makes cr_alignment a constant 0 to break code that tries to modify
the value as it's likely that it's built on wrong assumption when
CONFIG_CPU_CP15 isn't defined. For code that is only reading the value 0
is more or less a fine value to report.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Message-Id: 1358413196-5609-2-git-send-email-u.kleine-koenig@pengutronix.de (v8)
This commit is contained in:
Uwe Kleine-König 2012-01-16 10:34:31 +01:00
parent 949db153b6
commit b849a60e09
4 changed files with 41 additions and 3 deletions
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16
arch/arm/include/asm/cp15.h
View File

@ -42,6 +42,8 @@
#define vectors_high() (0)
#endif
#ifdef CONFIG_CPU_CP15
extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
extern unsigned long cr_alignment; /* defined in entry-armv.S */
@ -82,6 +84,18 @@ static inline void set_copro_access(unsigned int val)
isb();
}
#endif
#else /* ifdef CONFIG_CPU_CP15 */
/*
* cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
* minds of the developers). Yielding 0 for machines without a cp15 (and making
* it read-only) is fine for most cases and saves quite some #ifdeffery.
*/
#define cr_no_alignment UL(0)
#define cr_alignment UL(0)
#endif /* ifdef CONFIG_CPU_CP15 / else */
#endif /* ifndef __ASSEMBLY__ */
#endif

9
arch/arm/kernel/head-common.S
View File

@ -98,8 +98,9 @@ __mmap_switched:
str r9, [r4] @ Save processor ID
str r1, [r5] @ Save machine type
str r2, [r6] @ Save atags pointer
bic r4, r0, #CR_A @ Clear 'A' bit
stmia r7, {r0, r4} @ Save control register values
cmp r7, #0
bicne r4, r0, #CR_A @ Clear 'A' bit
stmneia r7, {r0, r4} @ Save control register values
b start_kernel
ENDPROC(__mmap_switched)
@ -113,7 +114,11 @@ __mmap_switched_data:
.long processor_id @ r4
.long __machine_arch_type @ r5
.long __atags_pointer @ r6
#ifdef CONFIG_CPU_CP15
.long cr_alignment @ r7
#else
.long 0 @ r7
#endif
.long init_thread_union + THREAD_START_SP @ sp
.size __mmap_switched_data, . - __mmap_switched_data

2
arch/arm/mm/alignment.c
View File

@ -964,12 +964,14 @@ static int __init alignment_init(void)
return -ENOMEM;
#endif
#ifdef CONFIG_CPU_CP15
if (cpu_is_v6_unaligned()) {
cr_alignment &= ~CR_A;
cr_no_alignment &= ~CR_A;
set_cr(cr_alignment);
ai_usermode = safe_usermode(ai_usermode, false);
}
#endif
hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
"alignment exception");

17
arch/arm/mm/mmu.c
View File

@ -97,6 +97,7 @@ static struct cachepolicy cache_policies[] __initdata = {
}
};
#ifdef CONFIG_CPU_CP15
/*
* These are useful for identifying cache coherency
* problems by allowing the cache or the cache and
@ -195,6 +196,22 @@ void adjust_cr(unsigned long mask, unsigned long set)
}
#endif
#else /* ifdef CONFIG_CPU_CP15 */
static int __init early_cachepolicy(char *p)
{
pr_warning("cachepolicy kernel parameter not supported without cp15\n");
}
early_param("cachepolicy", early_cachepolicy);
static int __init noalign_setup(char *__unused)
{
pr_warning("noalign kernel parameter not supported without cp15\n");
}
__setup("noalign", noalign_setup);
#endif /* ifdef CONFIG_CPU_CP15 / else */
#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE