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powerpc/8xx: Use SPRG2 instead of DAR for saving r3

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We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe 2015-04-20 07:54:44 +02:00 committed by Scott Wood
parent 2eb2fd9500
commit b821c5fe84
1 changed files with 4 additions and 5 deletions
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9
arch/powerpc/kernel/head_8xx.S
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@ -309,7 +309,7 @@ SystemCall:
InstructionTLBMiss: InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
mtspr SPRN_DAR, r3 mtspr SPRN_SPRG_SCRATCH2, r3
#endif #endif
EXCEPTION_PROLOG_0 EXCEPTION_PROLOG_0
@ -362,8 +362,7 @@ InstructionTLBMiss:
/* Restore registers */ /* Restore registers */
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
mfspr r3, SPRN_DAR mfspr r3, SPRN_SPRG_SCRATCH2
mtspr SPRN_DAR, r11 /* Tag DAR */
#endif #endif
EXCEPTION_EPILOG_0 EXCEPTION_EPILOG_0
rfi rfi
@ -371,7 +370,7 @@ InstructionTLBMiss:
. = 0x1200 . = 0x1200
DataStoreTLBMiss: DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
mtspr SPRN_DAR, r3 mtspr SPRN_SPRG_SCRATCH2, r3
#endif #endif
EXCEPTION_PROLOG_0 EXCEPTION_PROLOG_0
mfcr r10 mfcr r10
@ -438,7 +437,7 @@ DataStoreTLBMiss:
/* Restore registers */ /* Restore registers */
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
mfspr r3, SPRN_DAR mfspr r3, SPRN_SPRG_SCRATCH2
#endif #endif
mtspr SPRN_DAR, r11 /* Tag DAR */ mtspr SPRN_DAR, r11 /* Tag DAR */
EXCEPTION_EPILOG_0 EXCEPTION_EPILOG_0