drm/amd/display: move dsc clock from plane_resource to stream_resource
code restructure. Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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				| @ -2204,7 +2204,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, | ||||
| 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = | ||||
| 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; | ||||
| #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT | ||||
| 		context->res_ctx.pipe_ctx[i].plane_res.bw.dscclk_khz = | ||||
| 		context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz = | ||||
| 				context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000; | ||||
| #endif | ||||
| 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; | ||||
|  | ||||
| @ -222,15 +222,14 @@ struct resource_pool { | ||||
| 
 | ||||
| struct dcn_fe_bandwidth { | ||||
| 	int dppclk_khz; | ||||
| #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT | ||||
| 	int dscclk_khz; | ||||
| #endif | ||||
| 
 | ||||
| }; | ||||
| 
 | ||||
| struct stream_resource { | ||||
| 	struct output_pixel_processor *opp; | ||||
| #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT | ||||
| 	struct display_stream_compressor *dsc; | ||||
| 	int dscclk_khz; | ||||
| #endif | ||||
| 	struct timing_generator *tg; | ||||
| 	struct stream_encoder *stream_enc; | ||||
|  | ||||
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