Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' and 'clk-renesas' into clk-next

- Add support to get duty cycle of generic pwm clks

* clk-pwm-duty:
  clk: pwm: implement the .get_duty_cycle callback

* clk-bcm:
  clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB
  clk: bcm: Make BCM2835 clock drivers selectable

* clk-mtk:
  clk: mediatek: Remove MT8183 unused clock
  clk: mediatek: add audsys clock driver for MT8516
  dt-bindings: mediatek: audsys: add support for MT8516

* clk-qcom-msm8998-gpu:
  dt-bindings: clock: Document gpucc for msm8998

* clk-renesas:
  clk: renesas: cpg-mssr: Use [] to denote a flexible array member
  clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
  clk: renesas: mstp: Combine group-private and clock array allocation
  clk: renesas: div6: Combine clock-private and parent array allocation
  clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
  clk: renesas: r8a774a1: Add TMU clock
  clk: renesas: r8a77995: Add CMM clocks
  clk: renesas: r8a77990: Add CMM clocks
  clk: renesas: r8a77965: Add CMM clocks
  clk: renesas: r8a7795: Add CMM clocks
  clk: renesas: r9a06g032: Add clock domain support
  dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains
  clk: renesas: mstp: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
  clk: renesas: r8a7796: Add CMM clocks
  clk: renesas: r8a779{5|6|65}: Add TPU clock

include/dt-bindings/clock/mt8516-clk.h

@@ -208,4 +208,21 @@
 #define CLK_TOP_MSDC2_INFRA		176
 #define CLK_TOP_NR_CLK			177
 
+/* AUDSYS */
+
+#define CLK_AUD_AFE			0
+#define CLK_AUD_I2S			1
+#define CLK_AUD_22M			2
+#define CLK_AUD_24M			3
+#define CLK_AUD_INTDIR			4
+#define CLK_AUD_APLL2_TUNER		5
+#define CLK_AUD_APLL_TUNER		6
+#define CLK_AUD_HDMI			7
+#define CLK_AUD_SPDF			8
+#define CLK_AUD_ADC			9
+#define CLK_AUD_DAC			10
+#define CLK_AUD_DAC_PREDIS		11
+#define CLK_AUD_TML			12
+#define CLK_AUD_NR_CLK			13
+
 #endif /* _DT_BINDINGS_CLK_MT8516_H */

include/dt-bindings/clock/qcom,gpucc-msm8998.h

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, Jeffrey Hugo
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H
+#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H
+
+#define GPUPLL0						0
+#define GPUPLL0_OUT_EVEN				1
+#define RBCPR_CLK_SRC					2
+#define GFX3D_CLK_SRC					3
+#define RBBMTIMER_CLK_SRC				4
+#define GFX3D_ISENSE_CLK_SRC				5
+#define RBCPR_CLK					6
+#define GFX3D_CLK					7
+#define RBBMTIMER_CLK					8
+#define GFX3D_ISENSE_CLK				9
+#define GPUCC_CXO_CLK					10
+
+#define GPU_CX_BCR					0
+#define RBCPR_BCR					1
+#define GPU_GX_BCR					2
+#define GPU_ISENSE_BCR					3
+
+#define GPU_CX_GDSC					1
+#define GPU_GX_GDSC					2
+
+#endif