Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' and 'clk-renesas' into clk-next
- Add support to get duty cycle of generic pwm clks
* clk-pwm-duty:
clk: pwm: implement the .get_duty_cycle callback
* clk-bcm:
clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB
clk: bcm: Make BCM2835 clock drivers selectable
* clk-mtk:
clk: mediatek: Remove MT8183 unused clock
clk: mediatek: add audsys clock driver for MT8516
dt-bindings: mediatek: audsys: add support for MT8516
* clk-qcom-msm8998-gpu:
dt-bindings: clock: Document gpucc for msm8998
* clk-renesas:
clk: renesas: cpg-mssr: Use [] to denote a flexible array member
clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
clk: renesas: mstp: Combine group-private and clock array allocation
clk: renesas: div6: Combine clock-private and parent array allocation
clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
clk: renesas: r8a774a1: Add TMU clock
clk: renesas: r8a77995: Add CMM clocks
clk: renesas: r8a77990: Add CMM clocks
clk: renesas: r8a77965: Add CMM clocks
clk: renesas: r8a7795: Add CMM clocks
clk: renesas: r9a06g032: Add clock domain support
dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains
clk: renesas: mstp: Remove error messages on out-of-memory conditions
clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions
clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
clk: renesas: r8a7796: Add CMM clocks
clk: renesas: r8a779{5|6|65}: Add TPU clock
This commit is contained in:
Stephen Boyd
commit
b6bb2bc2fd
@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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- "mediatek,mt8516-audsys", "syscon"
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- #clock-cells: Must be 1
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The AUDSYS controller uses the common clk binding from
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@ -2,13 +2,15 @@ Qualcomm Graphics Clock & Reset Controller Binding
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--------------------------------------------------
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Required properties :
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- compatible : shall contain "qcom,sdm845-gpucc"
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- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
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- reg : shall contain base register location and length
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- #clock-cells : from common clock binding, shall contain 1
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- #reset-cells : from common reset binding, shall contain 1
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- #power-domain-cells : from generic power domain binding, shall contain 1
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- clocks : shall contain the XO clock
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shall contain the gpll0 out main clock (msm8998)
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- clock-names : shall be "xo"
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shall be "gpll0" (msm8998)
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Example:
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gpucc: clock-controller@5090000 {
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@ -13,6 +13,7 @@ Required Properties:
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- external (optional) RGMII_REFCLK
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- clock-names: Must be:
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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- #power-domain-cells: Must be 0
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Examples
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--------
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@ -27,6 +28,7 @@ Examples
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clocks = <&ext_mclk>, <&ext_rtc_clk>,
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<&ext_jtag_clk>, <&ext_rgmii_ref>;
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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#power-domain-cells = <0>;
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};
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- Other nodes can use the clocks provided by SYSCTRL as in:
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@ -38,6 +40,7 @@ Examples
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART0>;
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clock-names = "baudclk";
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clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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power-domains = <&sysctrl>;
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};
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@ -1,3 +1,12 @@
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config CLK_BCM2835
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bool "Broadcom BCM2835 clock support"
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depends on ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST
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depends on COMMON_CLK
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default ARCH_BCM2835 || ARCH_BRCMSTB
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help
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Enable common clock framework support for Broadcom BCM2835
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SoCs.
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config CLK_BCM_63XX
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bool "Broadcom BCM63xx clock support"
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depends on ARCH_BCM_63XX || COMPILE_TEST
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@ -5,8 +5,8 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
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obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
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obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835-aux.o
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obj-$(CONFIG_CLK_BCM2835) += clk-bcm2835.o
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obj-$(CONFIG_CLK_BCM2835) += clk-bcm2835-aux.o
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obj-$(CONFIG_ARCH_BCM_53573) += clk-bcm53573-ilp.o
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obj-$(CONFIG_CLK_BCM_CYGNUS) += clk-cygnus.o
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obj-$(CONFIG_CLK_BCM_HR2) += clk-hr2.o
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@ -299,4 +299,10 @@ config COMMON_CLK_MT8516
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help
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This driver supports MediaTek MT8516 clocks.
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config COMMON_CLK_MT8516_AUDSYS
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bool "Clock driver for MediaTek MT8516 audsys"
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depends on COMMON_CLK_MT8516
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help
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This driver supports MediaTek MT8516 audsys clocks.
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endmenu
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@ -45,3 +45,4 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
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obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
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obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
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@ -395,14 +395,6 @@ static const char * const atb_parents[] = {
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"syspll_d5"
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};
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static const char * const sspm_parents[] = {
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"clk26m",
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"univpll_d2_d4",
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"syspll_d2_d2",
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"univpll_d2_d2",
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"syspll_d3"
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};
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static const char * const dpi0_parents[] = {
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"clk26m",
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"tvdpll_d2",
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@ -606,9 +598,6 @@ static const struct mtk_mux top_muxes[] = {
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
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atb_parents, 0xa0,
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0xa4, 0xa8, 0, 2, 7, 0x004, 24),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSPM, "sspm_sel",
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sspm_parents, 0xa0,
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0xa4, 0xa8, 8, 3, 15, 0x004, 25),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
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dpi0_parents, 0xa0,
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0xa4, 0xa8, 16, 4, 23, 0x004, 26),
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@ -947,12 +936,8 @@ static const struct mtk_gate infra_clks[] = {
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"fufs_sel", 13),
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GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
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"axi_sel", 14),
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GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm",
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"sspm_sel", 15),
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GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
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"axi_sel", 16),
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GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
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"axi_sel", 17),
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GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
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"i2c_sel", 18),
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GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
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@ -986,10 +971,6 @@ static const struct mtk_gate infra_clks[] = {
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"msdc50_0_sel", 1),
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GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
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"msdc50_0_sel", 2),
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GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
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"f_f26m_ck", 3),
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GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
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"f_f26m_ck", 4),
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GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
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"axi_sel", 5),
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GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
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65
drivers/clk/mediatek/clk-mt8516-aud.c
Normal file
65
drivers/clk/mediatek/clk-mt8516-aud.c
Normal file
@ -0,0 +1,65 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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* Fabien Parent <fparent@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8516-clk.h>
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static const struct mtk_gate_regs aud_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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#define GATE_AUD(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &aud_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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}
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static const struct mtk_gate aud_clks[] __initconst = {
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GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
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GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
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GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
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GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
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GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
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GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
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GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
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GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
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GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
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GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
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GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
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GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
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GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
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};
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static void __init mtk_audsys_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
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mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);
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@ -30,8 +30,8 @@
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* @div: divisor value (1-64)
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* @src_shift: Shift to access the register bits to select the parent clock
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* @src_width: Number of register bits to select the parent clock (may be 0)
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* @parents: Array to map from valid parent clocks indices to hardware indices
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* @nb: Notifier block to save/restore clock state for system resume
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* @parents: Array to map from valid parent clocks indices to hardware indices
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*/
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struct div6_clock {
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struct clk_hw hw;
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@ -39,8 +39,8 @@ struct div6_clock {
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unsigned int div;
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u32 src_shift;
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u32 src_width;
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u8 *parents;
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struct notifier_block nb;
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u8 parents[];
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};
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|
||||
#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
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@ -221,17 +221,10 @@ struct clk * __init cpg_div6_register(const char *name,
|
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struct clk *clk;
|
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unsigned int i;
|
||||
|
||||
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
|
||||
clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);
|
||||
if (!clock)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
|
||||
GFP_KERNEL);
|
||||
if (!clock->parents) {
|
||||
clk = ERR_PTR(-ENOMEM);
|
||||
goto free_clock;
|
||||
}
|
||||
|
||||
clock->reg = reg;
|
||||
|
||||
/*
|
||||
@ -259,7 +252,7 @@ struct clk * __init cpg_div6_register(const char *name,
|
||||
pr_err("%s: invalid number of parents for DIV6 clock %s\n",
|
||||
__func__, name);
|
||||
clk = ERR_PTR(-EINVAL);
|
||||
goto free_parents;
|
||||
goto free_clock;
|
||||
}
|
||||
|
||||
/* Filter out invalid parents */
|
||||
@ -282,7 +275,7 @@ struct clk * __init cpg_div6_register(const char *name,
|
||||
|
||||
clk = clk_register(NULL, &clock->hw);
|
||||
if (IS_ERR(clk))
|
||||
goto free_parents;
|
||||
goto free_clock;
|
||||
|
||||
if (notifiers) {
|
||||
clock->nb.notifier_call = cpg_div6_clock_notifier_call;
|
||||
@ -291,8 +284,6 @@ struct clk * __init cpg_div6_register(const char *name,
|
||||
|
||||
return clk;
|
||||
|
||||
free_parents:
|
||||
kfree(clock->parents);
|
||||
free_clock:
|
||||
kfree(clock);
|
||||
return clk;
|
||||
|
||||
@ -30,11 +30,12 @@
|
||||
/**
|
||||
* struct mstp_clock_group - MSTP gating clocks group
|
||||
*
|
||||
* @data: clocks in this group
|
||||
* @data: clock specifier translation for clocks in this group
|
||||
* @smstpcr: module stop control register
|
||||
* @mstpsr: module stop status register (optional)
|
||||
* @lock: protects writes to SMSTPCR
|
||||
* @width_8bit: registers are 8-bit, not 32-bit
|
||||
* @clks: clocks in this group
|
||||
*/
|
||||
struct mstp_clock_group {
|
||||
struct clk_onecell_data data;
|
||||
@ -42,6 +43,7 @@ struct mstp_clock_group {
|
||||
void __iomem *mstpsr;
|
||||
spinlock_t lock;
|
||||
bool width_8bit;
|
||||
struct clk *clks[];
|
||||
};
|
||||
|
||||
/**
|
||||
@ -186,14 +188,13 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
|
||||
group = kzalloc(sizeof(*group), GFP_KERNEL);
|
||||
clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL);
|
||||
if (group == NULL || clks == NULL) {
|
||||
group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
|
||||
if (group == NULL) {
|
||||
kfree(group);
|
||||
kfree(clks);
|
||||
return;
|
||||
}
|
||||
|
||||
clks = group->clks;
|
||||
spin_lock_init(&group->lock);
|
||||
group->data.clks = clks;
|
||||
|
||||
@ -203,7 +204,6 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
|
||||
if (group->smstpcr == NULL) {
|
||||
pr_err("%s: failed to remap SMSTPCR\n", __func__);
|
||||
kfree(group);
|
||||
kfree(clks);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -297,16 +297,12 @@ found:
|
||||
return PTR_ERR(clk);
|
||||
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_create failed %d\n", error);
|
||||
if (error)
|
||||
goto fail_put;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
|
||||
if (error)
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@ -113,6 +113,11 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
|
||||
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
|
||||
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
|
||||
DEF_MOD("tmu1", 124, R8A774A1_CLK_S3D2),
|
||||
DEF_MOD("tmu0", 125, R8A774A1_CLK_CP),
|
||||
DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
|
||||
|
||||
@ -138,6 +138,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
|
||||
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
|
||||
@ -201,6 +202,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
|
||||
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
|
||||
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
|
||||
|
||||
@ -134,6 +134,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
|
||||
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A7796_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
|
||||
@ -180,6 +181,9 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
|
||||
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
|
||||
|
||||
@ -132,6 +132,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
||||
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77965_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
|
||||
@ -179,6 +180,9 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
||||
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
|
||||
|
||||
@ -183,6 +183,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
||||
|
||||
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("cmm1", 710, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("cmm0", 711, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
|
||||
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
|
||||
|
||||
@ -146,6 +146,8 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
||||
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
|
||||
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
|
||||
@ -17,6 +17,8 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
|
||||
@ -29,6 +31,7 @@ struct r9a06g032_gate {
|
||||
/* This is used to describe a clock for instantiation */
|
||||
struct r9a06g032_clkdesc {
|
||||
const char *name;
|
||||
uint32_t managed: 1;
|
||||
uint32_t type: 3;
|
||||
uint32_t index: 8;
|
||||
uint32_t source : 8; /* source index + 1 (0 == none) */
|
||||
@ -61,7 +64,11 @@ struct r9a06g032_clkdesc {
|
||||
#define D_GATE(_idx, _n, _src, ...) \
|
||||
{ .type = K_GATE, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.gate = I_GATE(__VA_ARGS__), }
|
||||
.gate = I_GATE(__VA_ARGS__) }
|
||||
#define D_MODULE(_idx, _n, _src, ...) \
|
||||
{ .type = K_GATE, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.managed = 1, .gate = I_GATE(__VA_ARGS__) }
|
||||
#define D_ROOT(_idx, _n, _mul, _div) \
|
||||
{ .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
|
||||
.div = _div, .mul = _mul }
|
||||
@ -122,7 +129,7 @@ enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
|
||||
|
||||
#define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1)
|
||||
|
||||
static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
|
||||
static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
|
||||
D_ROOT(CLKOUT, "clkout", 25, 1),
|
||||
D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
|
||||
D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
|
||||
@ -171,7 +178,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
|
||||
D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
|
||||
D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
|
||||
D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
|
||||
D_GATE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
|
||||
D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
|
||||
@ -188,17 +195,17 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
|
||||
D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
|
||||
D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
|
||||
D_GATE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
|
||||
D_GATE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
|
||||
D_GATE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
|
||||
D_GATE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
|
||||
D_GATE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
|
||||
D_GATE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
|
||||
D_GATE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
|
||||
D_GATE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
|
||||
D_GATE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
|
||||
D_GATE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
|
||||
D_GATE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
|
||||
D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
|
||||
D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
|
||||
D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
|
||||
D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
|
||||
D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
|
||||
D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
|
||||
D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
|
||||
D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
|
||||
D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
|
||||
D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
|
||||
@ -208,13 +215,13 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
|
||||
D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
|
||||
D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
|
||||
D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
|
||||
D_GATE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
|
||||
D_GATE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
|
||||
D_GATE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
|
||||
D_GATE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
|
||||
D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
|
||||
D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
|
||||
D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
|
||||
D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
|
||||
D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
|
||||
@ -222,53 +229,53 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
|
||||
D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
|
||||
D_GATE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
|
||||
D_GATE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
|
||||
D_GATE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
|
||||
D_GATE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
|
||||
D_GATE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
|
||||
D_GATE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
|
||||
D_GATE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
|
||||
D_GATE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
|
||||
D_GATE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
|
||||
D_GATE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
|
||||
D_GATE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
|
||||
D_GATE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
|
||||
D_GATE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
|
||||
D_GATE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
|
||||
D_GATE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
|
||||
D_GATE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
|
||||
D_GATE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
|
||||
D_GATE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
|
||||
D_GATE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
|
||||
D_GATE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
|
||||
D_GATE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
|
||||
D_GATE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
|
||||
D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
|
||||
D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
|
||||
D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
|
||||
D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
|
||||
D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
|
||||
D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
|
||||
D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
|
||||
D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
|
||||
D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
|
||||
D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
|
||||
D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
|
||||
D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
|
||||
D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
|
||||
D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
|
||||
D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
|
||||
D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
|
||||
D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
|
||||
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
|
||||
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
|
||||
D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
|
||||
D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
|
||||
/*
|
||||
* These are not hardware clocks, but are needed to handle the special
|
||||
* case where we have a 'selector bit' that doesn't just change the
|
||||
@ -345,6 +352,84 @@ struct r9a06g032_clk_gate {
|
||||
|
||||
#define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw)
|
||||
|
||||
static int create_add_module_clock(struct of_phandle_args *clkspec,
|
||||
struct device *dev)
|
||||
{
|
||||
struct clk *clk;
|
||||
int error;
|
||||
|
||||
clk = of_clk_get_from_provider(clkspec);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
clk_put(clk);
|
||||
return error;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
pm_clk_destroy(dev);
|
||||
clk_put(clk);
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
|
||||
struct device *dev)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
int i = 0;
|
||||
int error;
|
||||
int index;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (clkspec.np != pd->dev.of_node)
|
||||
continue;
|
||||
|
||||
index = clkspec.args[0];
|
||||
if (index < R9A06G032_CLOCK_COUNT &&
|
||||
r9a06g032_clocks[index].managed) {
|
||||
error = create_add_module_clock(&clkspec, dev);
|
||||
of_node_put(clkspec.np);
|
||||
if (error)
|
||||
return error;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
if (!pm_clk_no_clocks(dev))
|
||||
pm_clk_destroy(dev);
|
||||
}
|
||||
|
||||
static int r9a06g032_add_clk_domain(struct device *dev)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct generic_pm_domain *pd;
|
||||
|
||||
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
pd->name = np->name;
|
||||
pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
pd->attach_dev = r9a06g032_attach_dev;
|
||||
pd->detach_dev = r9a06g032_detach_dev;
|
||||
pm_genpd_init(pd, &pm_domain_always_on_gov, false);
|
||||
|
||||
of_genpd_add_provider_simple(np, pd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
|
||||
struct r9a06g032_gate *g, int on)
|
||||
@ -871,8 +956,12 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
return devm_add_action_or_reset(dev,
|
||||
error = devm_add_action_or_reset(dev,
|
||||
r9a06g032_clocks_del_clk_provider, np);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
return r9a06g032_add_clk_domain(dev);
|
||||
}
|
||||
|
||||
static const struct of_device_id r9a06g032_match[] = {
|
||||
|
||||
@ -112,14 +112,15 @@ static const u16 srcr[] = {
|
||||
* @dev: CPG/MSSR device
|
||||
* @base: CPG/MSSR register block base address
|
||||
* @rmw_lock: protects RMW register accesses
|
||||
* @clks: Array containing all Core and Module Clocks
|
||||
* @np: Device node in DT for this CPG/MSSR module
|
||||
* @num_core_clks: Number of Core Clocks in clks[]
|
||||
* @num_mod_clks: Number of Module Clocks in clks[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @stbyctrl: This device has Standby Control Registers
|
||||
* @notifiers: Notifier chain to save/restore clock state for system resume
|
||||
* @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
|
||||
* @smstpcr_saved[].val: Saved values of SMSTPCR[]
|
||||
* @stbyctrl: This device has Standby Control Registers
|
||||
* @clks: Array containing all Core and Module Clocks
|
||||
*/
|
||||
struct cpg_mssr_priv {
|
||||
#ifdef CONFIG_RESET_CONTROLLER
|
||||
@ -130,7 +131,6 @@ struct cpg_mssr_priv {
|
||||
spinlock_t rmw_lock;
|
||||
struct device_node *np;
|
||||
|
||||
struct clk **clks;
|
||||
unsigned int num_core_clks;
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
@ -141,6 +141,8 @@ struct cpg_mssr_priv {
|
||||
u32 mask;
|
||||
u32 val;
|
||||
} smstpcr_saved[ARRAY_SIZE(smstpcr)];
|
||||
|
||||
struct clk *clks[];
|
||||
};
|
||||
|
||||
static struct cpg_mssr_priv *cpg_mssr_priv;
|
||||
@ -447,9 +449,8 @@ fail:
|
||||
|
||||
struct cpg_mssr_clk_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
struct device_node *np;
|
||||
unsigned int num_core_pm_clks;
|
||||
unsigned int core_pm_clks[0];
|
||||
unsigned int core_pm_clks[];
|
||||
};
|
||||
|
||||
static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
|
||||
@ -459,7 +460,7 @@ static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (clkspec->np != pd->np || clkspec->args_count != 2)
|
||||
if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
|
||||
return false;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
@ -510,16 +511,12 @@ found:
|
||||
return PTR_ERR(clk);
|
||||
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_create failed %d\n", error);
|
||||
if (error)
|
||||
goto fail_put;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
|
||||
if (error)
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -549,7 +546,6 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
pd->np = np;
|
||||
pd->num_core_pm_clks = num_core_pm_clks;
|
||||
memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
|
||||
|
||||
@ -896,7 +892,6 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
||||
const struct cpg_mssr_info *info)
|
||||
{
|
||||
struct cpg_mssr_priv *priv;
|
||||
struct clk **clks = NULL;
|
||||
unsigned int nclks, i;
|
||||
int error;
|
||||
|
||||
@ -906,7 +901,8 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
||||
return error;
|
||||
}
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
||||
priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -920,15 +916,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
||||
clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
error = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
cpg_mssr_priv = priv;
|
||||
priv->clks = clks;
|
||||
priv->num_core_clks = info->num_total_core_clks;
|
||||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
@ -936,7 +924,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
||||
priv->stbyctrl = info->stbyctrl;
|
||||
|
||||
for (i = 0; i < nclks; i++)
|
||||
clks[i] = ERR_PTR(-ENOENT);
|
||||
priv->clks[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
|
||||
if (error)
|
||||
@ -945,7 +933,6 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
||||
return 0;
|
||||
|
||||
out_err:
|
||||
kfree(clks);
|
||||
if (priv->base)
|
||||
iounmap(priv->base);
|
||||
kfree(priv);
|
||||
|
||||
@ -208,4 +208,21 @@
|
||||
#define CLK_TOP_MSDC2_INFRA 176
|
||||
#define CLK_TOP_NR_CLK 177
|
||||
|
||||
/* AUDSYS */
|
||||
|
||||
#define CLK_AUD_AFE 0
|
||||
#define CLK_AUD_I2S 1
|
||||
#define CLK_AUD_22M 2
|
||||
#define CLK_AUD_24M 3
|
||||
#define CLK_AUD_INTDIR 4
|
||||
#define CLK_AUD_APLL2_TUNER 5
|
||||
#define CLK_AUD_APLL_TUNER 6
|
||||
#define CLK_AUD_HDMI 7
|
||||
#define CLK_AUD_SPDF 8
|
||||
#define CLK_AUD_ADC 9
|
||||
#define CLK_AUD_DAC 10
|
||||
#define CLK_AUD_DAC_PREDIS 11
|
||||
#define CLK_AUD_TML 12
|
||||
#define CLK_AUD_NR_CLK 13
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8516_H */
|
||||
|
||||
29
include/dt-bindings/clock/qcom,gpucc-msm8998.h
Normal file
29
include/dt-bindings/clock/qcom,gpucc-msm8998.h
Normal file
@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019, Jeffrey Hugo
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H
|
||||
#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H
|
||||
|
||||
#define GPUPLL0 0
|
||||
#define GPUPLL0_OUT_EVEN 1
|
||||
#define RBCPR_CLK_SRC 2
|
||||
#define GFX3D_CLK_SRC 3
|
||||
#define RBBMTIMER_CLK_SRC 4
|
||||
#define GFX3D_ISENSE_CLK_SRC 5
|
||||
#define RBCPR_CLK 6
|
||||
#define GFX3D_CLK 7
|
||||
#define RBBMTIMER_CLK 8
|
||||
#define GFX3D_ISENSE_CLK 9
|
||||
#define GPUCC_CXO_CLK 10
|
||||
|
||||
#define GPU_CX_BCR 0
|
||||
#define RBCPR_BCR 1
|
||||
#define GPU_GX_BCR 2
|
||||
#define GPU_ISENSE_BCR 3
|
||||
|
||||
#define GPU_CX_GDSC 1
|
||||
#define GPU_GX_GDSC 2
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user