leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[POWERPC] 4xx: Only reset PCIe PHY on 405EX systems when no link is detected

Browse Source 
Since the arch/powerpc PCI subsystem now does a complete re-assignment of
the resources, we can move from the unconditional PCIe PHY reset to the
conditional version. Now the PHY is only reset, if no link is established yet.
An additional PHY reset (one is already done in U-Boot) leads to problems
with some Atheros PCIe boards and some HP FPGA PCIe designs.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Stefan Roese 2008-03-28 02:34:50 +11:00 committed by Josh Boyer
parent e04018e8e4
commit b64c4c937d
1 changed files with 0 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/powerpc/sysdev/ppc4xx_pci.c
View File

@ -940,17 +940,9 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
* PCIe boards don't show this problem.
* This has to be re-tested and fixed in a later release!
*/
#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
* configured as done previously by U-Boot. Then Linux will currently
* not reassign them. So the PHY reset is now done always. This will
* lead to problems with the Atheros PCIe board again.
*/
val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
if (!(val & 0x00001000))
ppc405ex_pcie_phy_reset(port);
#else
ppc405ex_pcie_phy_reset(port);
#endif
dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */