drm/amdgpu: only move VM BOs in the LRU during validation v2
This should save us a bunch of command submission overhead. v2: move the LRU move to the right place to avoid the move for the root BO and handle the shadow BOs as well. This turned out to be a bug fix because the move needs to happen before the kmap. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -673,10 +673,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
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}
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error_validate:
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if (r) {
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amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
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if (r)
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ttm_eu_backoff_reservation(&p->ticket, &p->validated);
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}
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error_free_pages:
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@ -724,21 +722,18 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
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* If error is set than unvalidate buffer, otherwise just free memory
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* used by parsing context.
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**/
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static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
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static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
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bool backoff)
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{
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struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
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unsigned i;
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if (!error) {
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amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
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if (!error)
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ttm_eu_fence_buffer_objects(&parser->ticket,
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&parser->validated,
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parser->fence);
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} else if (backoff) {
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else if (backoff)
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ttm_eu_backoff_reservation(&parser->ticket,
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&parser->validated);
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}
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for (i = 0; i < parser->num_post_dep_syncobjs; i++)
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drm_syncobj_put(parser->post_dep_syncobjs[i]);
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@ -159,7 +159,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
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*/
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static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
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int (*validate)(void *, struct amdgpu_bo *),
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void *param, bool use_cpu_for_update)
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void *param, bool use_cpu_for_update,
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struct ttm_bo_global *glob)
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{
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unsigned i;
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int r;
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@ -183,12 +184,18 @@ static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
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if (r)
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return r;
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spin_lock(&glob->lru_lock);
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ttm_bo_move_to_lru_tail(&entry->bo->tbo);
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if (entry->bo->shadow)
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ttm_bo_move_to_lru_tail(&entry->bo->shadow->tbo);
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spin_unlock(&glob->lru_lock);
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/*
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* Recurse into the sub directory. This is harmless because we
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* have only a maximum of 5 layers.
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*/
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r = amdgpu_vm_validate_level(entry, validate, param,
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use_cpu_for_update);
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use_cpu_for_update, glob);
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if (r)
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return r;
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}
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@ -220,54 +227,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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return 0;
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return amdgpu_vm_validate_level(&vm->root, validate, param,
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vm->use_cpu_for_update);
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vm->use_cpu_for_update,
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adev->mman.bdev.glob);
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}
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/**
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* amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail
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*
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* @adev: amdgpu device instance
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* @vm: vm providing the BOs
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*
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* Move the PT BOs to the tail of the LRU.
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*/
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static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent)
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{
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unsigned i;
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if (!parent->entries)
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return;
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for (i = 0; i <= parent->last_entry_used; ++i) {
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struct amdgpu_vm_pt *entry = &parent->entries[i];
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if (!entry->bo)
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continue;
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ttm_bo_move_to_lru_tail(&entry->bo->tbo);
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amdgpu_vm_move_level_in_lru(entry);
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}
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}
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/**
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* amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
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*
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* @adev: amdgpu device instance
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* @vm: vm providing the BOs
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*
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* Move the PT BOs to the tail of the LRU.
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*/
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void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
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struct amdgpu_vm *vm)
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{
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struct ttm_bo_global *glob = adev->mman.bdev.glob;
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spin_lock(&glob->lru_lock);
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amdgpu_vm_move_level_in_lru(&vm->root);
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spin_unlock(&glob->lru_lock);
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}
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/**
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* amdgpu_vm_alloc_levels - allocate the PD/PT levels
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*
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* @adev: amdgpu_device pointer
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@ -223,8 +223,6 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
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int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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int (*callback)(void *p, struct amdgpu_bo *bo),
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void *param);
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void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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uint64_t saddr, uint64_t size);
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