forked from Minki/linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
This commit is contained in:
David S. Miller
commit
b45efa30a6
1
.mailmap
1
.mailmap
@ -21,6 +21,7 @@ Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
|
||||
Andrew Morton <akpm@linux-foundation.org>
|
||||
Andrew Vasquez <andrew.vasquez@qlogic.com>
|
||||
Andy Adamson <andros@citi.umich.edu>
|
||||
Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>
|
||||
Archit Taneja <archit@ti.com>
|
||||
Arnaud Patard <arnaud.patard@rtp-net.org>
|
||||
Arnd Bergmann <arnd@arndb.de>
|
||||
|
||||
10
CREDITS
10
CREDITS
@ -1856,6 +1856,16 @@ S: Korte Heul 95
|
||||
S: 1403 ND BUSSUM
|
||||
S: The Netherlands
|
||||
|
||||
N: Martin Kepplinger
|
||||
E: martink@posteo.de
|
||||
E: martin.kepplinger@theobroma-systems.com
|
||||
W: http://www.martinkepplinger.com
|
||||
D: mma8452 accelerators iio driver
|
||||
D: Kernel cleanups
|
||||
S: Garnisonstraße 26
|
||||
S: 4020 Linz
|
||||
S: Austria
|
||||
|
||||
N: Karl Keyte
|
||||
E: karl@koft.com
|
||||
D: Disk usage statistics and modifications to line printer driver
|
||||
|
||||
22
Documentation/ABI/testing/configfs-rdma_cm
Normal file
22
Documentation/ABI/testing/configfs-rdma_cm
Normal file
@ -0,0 +1,22 @@
|
||||
What: /config/rdma_cm
|
||||
Date: November 29, 2015
|
||||
KernelVersion: 4.4.0
|
||||
Description: Interface is used to configure RDMA-cable HCAs in respect to
|
||||
RDMA-CM attributes.
|
||||
|
||||
Attributes are visible only when configfs is mounted. To mount
|
||||
configfs in /config directory use:
|
||||
# mount -t configfs none /config/
|
||||
|
||||
In order to set parameters related to a specific HCA, a directory
|
||||
for this HCA has to be created:
|
||||
mkdir -p /config/rdma_cm/<hca>
|
||||
|
||||
|
||||
What: /config/rdma_cm/<hca>/ports/<port-num>/default_roce_mode
|
||||
Date: November 29, 2015
|
||||
KernelVersion: 4.4.0
|
||||
Description: RDMA-CM based connections from HCA <hca> at port <port-num>
|
||||
will be initiated with this RoCE type as default.
|
||||
The possible RoCE types are either "IB/RoCE v1" or "RoCE v2".
|
||||
This parameter has RW access.
|
||||
6
Documentation/ABI/testing/configfs-usb-gadget-tcm
Normal file
6
Documentation/ABI/testing/configfs-usb-gadget-tcm
Normal file
@ -0,0 +1,6 @@
|
||||
What: /config/usb-gadget/gadget/functions/tcm.name
|
||||
Date: Dec 2015
|
||||
KernelVersion: 4.5
|
||||
Description:
|
||||
There are no attributes because all the configuration
|
||||
is performed in the "target" subsystem of configfs.
|
||||
16
Documentation/ABI/testing/sysfs-class-infiniband
Normal file
16
Documentation/ABI/testing/sysfs-class-infiniband
Normal file
@ -0,0 +1,16 @@
|
||||
What: /sys/class/infiniband/<hca>/ports/<port-number>/gid_attrs/ndevs/<gid-index>
|
||||
Date: November 29, 2015
|
||||
KernelVersion: 4.4.0
|
||||
Contact: linux-rdma@vger.kernel.org
|
||||
Description: The net-device's name associated with the GID resides
|
||||
at index <gid-index>.
|
||||
|
||||
What: /sys/class/infiniband/<hca>/ports/<port-number>/gid_attrs/types/<gid-index>
|
||||
Date: November 29, 2015
|
||||
KernelVersion: 4.4.0
|
||||
Contact: linux-rdma@vger.kernel.org
|
||||
Description: The RoCE type of the associated GID resides at index <gid-index>.
|
||||
This could either be "IB/RoCE v1" for IB and RoCE v1 based GODs
|
||||
or "RoCE v2" for RoCE v2 based GIDs.
|
||||
|
||||
|
||||
51
Documentation/ABI/testing/sysfs-class-watchdog
Normal file
51
Documentation/ABI/testing/sysfs-class-watchdog
Normal file
@ -0,0 +1,51 @@
|
||||
What: /sys/class/watchdog/watchdogn/bootstatus
|
||||
Date: August 2015
|
||||
Contact: Wim Van Sebroeck <wim@iguana.be>
|
||||
Description:
|
||||
It is a read only file. It contains status of the watchdog
|
||||
device at boot. It is equivalent to WDIOC_GETBOOTSTATUS of
|
||||
ioctl interface.
|
||||
|
||||
What: /sys/class/watchdog/watchdogn/identity
|
||||
Date: August 2015
|
||||
Contact: Wim Van Sebroeck <wim@iguana.be>
|
||||
Description:
|
||||
It is a read only file. It contains identity string of
|
||||
watchdog device.
|
||||
|
||||
What: /sys/class/watchdog/watchdogn/nowayout
|
||||
Date: August 2015
|
||||
Contact: Wim Van Sebroeck <wim@iguana.be>
|
||||
Description:
|
||||
It is a read only file. While reading, it gives '1' if that
|
||||
device supports nowayout feature else, it gives '0'.
|
||||
|
||||
What: /sys/class/watchdog/watchdogn/state
|
||||
Date: August 2015
|
||||
Contact: Wim Van Sebroeck <wim@iguana.be>
|
||||
Description:
|
||||
It is a read only file. It gives active/inactive status of
|
||||
watchdog device.
|
||||
|
||||
What: /sys/class/watchdog/watchdogn/status
|
||||
Date: August 2015
|
||||
Contact: Wim Van Sebroeck <wim@iguana.be>
|
||||
Description:
|
||||
It is a read only file. It contains watchdog device's
|
||||
internal status bits. It is equivalent to WDIOC_GETSTATUS
|
||||
of ioctl interface.
|
||||
|
||||
What: /sys/class/watchdog/watchdogn/timeleft
|
||||
Date: August 2015
|
||||
Contact: Wim Van Sebroeck <wim@iguana.be>
|
||||
Description:
|
||||
It is a read only file. It contains value of time left for
|
||||
reset generation. It is equivalent to WDIOC_GETTIMELEFT of
|
||||
ioctl interface.
|
||||
|
||||
What: /sys/class/watchdog/watchdogn/timeout
|
||||
Date: August 2015
|
||||
Contact: Wim Van Sebroeck <wim@iguana.be>
|
||||
Description:
|
||||
It is a read only file. It is read to know about current
|
||||
value of timeout programmed.
|
||||
@ -430,7 +430,7 @@ The rationale for using gotos is:
|
||||
return result;
|
||||
}
|
||||
|
||||
A common type of bug to be aware of it "one err bugs" which look like this:
|
||||
A common type of bug to be aware of is "one err bugs" which look like this:
|
||||
|
||||
err:
|
||||
kfree(foo->bar);
|
||||
|
||||
@ -951,16 +951,6 @@ to "Closing".
|
||||
alignment constraints (e.g. the alignment constraints about 64-bit
|
||||
objects).
|
||||
|
||||
3) Supporting multiple types of IOMMUs
|
||||
|
||||
If your architecture needs to support multiple types of IOMMUs, you
|
||||
can use include/linux/asm-generic/dma-mapping-common.h. It's a
|
||||
library to support the DMA API with multiple types of IOMMUs. Lots
|
||||
of architectures (x86, powerpc, sh, alpha, ia64, microblaze and
|
||||
sparc) use it. Choose one to see how it can be used. If you need to
|
||||
support multiple types of IOMMUs in a single system, the example of
|
||||
x86 or powerpc helps.
|
||||
|
||||
Closing
|
||||
|
||||
This document, and the API itself, would not be in its current
|
||||
|
||||
@ -236,7 +236,7 @@ are guaranteed also to be cache line boundaries).
|
||||
|
||||
DMA_TO_DEVICE synchronisation must be done after the last modification
|
||||
of the memory region by the software and before it is handed off to
|
||||
the driver. Once this primitive is used, memory covered by this
|
||||
the device. Once this primitive is used, memory covered by this
|
||||
primitive should be treated as read-only by the device. If the device
|
||||
may write to it at any point, it should be DMA_BIDIRECTIONAL (see
|
||||
below).
|
||||
|
||||
@ -50,8 +50,7 @@ pdfdocs: $(PDF)
|
||||
|
||||
HTML := $(sort $(patsubst %.xml, %.html, $(BOOKS)))
|
||||
htmldocs: $(HTML)
|
||||
$(call build_main_index)
|
||||
$(call build_images)
|
||||
$(call cmd,build_main_index)
|
||||
$(call install_media_images)
|
||||
|
||||
MAN := $(patsubst %.xml, %.9, $(BOOKS))
|
||||
@ -139,7 +138,8 @@ quiet_cmd_db2pdf = PDF $@
|
||||
|
||||
index = index.html
|
||||
main_idx = $(obj)/$(index)
|
||||
build_main_index = rm -rf $(main_idx); \
|
||||
quiet_cmd_build_main_index = HTML $(main_idx)
|
||||
cmd_build_main_index = rm -rf $(main_idx); \
|
||||
echo '<h1>Linux Kernel HTML Documentation</h1>' >> $(main_idx) && \
|
||||
echo '<h2>Kernel Version: $(KERNELVERSION)</h2>' >> $(main_idx) && \
|
||||
cat $(HTML) >> $(main_idx)
|
||||
@ -227,6 +227,10 @@ dochelp:
|
||||
@echo ' mandocs - man pages'
|
||||
@echo ' installmandocs - install man pages generated by mandocs'
|
||||
@echo ' cleandocs - clean all generated DocBook files'
|
||||
@echo
|
||||
@echo 'make DOCBOOKS="s1.xml s2.xml" [target] Generate only docs s1.xml s2.xml'
|
||||
@echo ' valid values for DOCBOOKS are: $(DOCBOOKS)'
|
||||
|
||||
|
||||
###
|
||||
# Temporary files left by various tools
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -458,7 +458,7 @@
|
||||
.scan_type = {
|
||||
.sign = 's',
|
||||
.realbits = 12,
|
||||
.storgebits = 16,
|
||||
.storagebits = 16,
|
||||
.shift = 4,
|
||||
.endianness = IIO_LE,
|
||||
},
|
||||
|
||||
@ -209,7 +209,7 @@ tools. One such tool that is particularly recommended is the Linux
|
||||
Cross-Reference project, which is able to present source code in a
|
||||
self-referential, indexed webpage format. An excellent up-to-date
|
||||
repository of the kernel code may be found at:
|
||||
http://lxr.linux.no/+trees
|
||||
http://lxr.free-electrons.com/
|
||||
|
||||
|
||||
The development process
|
||||
|
||||
@ -3,7 +3,7 @@ Linux IOMMU Support
|
||||
|
||||
The architecture spec can be obtained from the below location.
|
||||
|
||||
http://www.intel.com/technology/virtualization/
|
||||
http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
|
||||
|
||||
This guide gives a quick cheat sheet for some basic understanding.
|
||||
|
||||
|
||||
@ -375,7 +375,8 @@ int main(int argc, char *argv[])
|
||||
}
|
||||
}
|
||||
|
||||
if ((nl_sd = create_nl_socket(NETLINK_GENERIC)) < 0)
|
||||
nl_sd = create_nl_socket(NETLINK_GENERIC);
|
||||
if (nl_sd < 0)
|
||||
err(1, "error creating Netlink socket\n");
|
||||
|
||||
|
||||
|
||||
@ -233,29 +233,30 @@ MMP/MMP2 family (communication processor)
|
||||
Linux kernel mach directory: arch/arm/mach-mmp
|
||||
Linux kernel plat directory: arch/arm/plat-pxa
|
||||
|
||||
Berlin family (Digital Entertainment)
|
||||
Berlin family (Multimedia Solutions)
|
||||
-------------------------------------
|
||||
|
||||
Flavors:
|
||||
88DE3005, Armada 1500-mini
|
||||
88DE3005, Armada 1500 Mini
|
||||
Design name: BG2CD
|
||||
Core: ARM Cortex-A9, PL310 L2CC
|
||||
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-mini/
|
||||
Homepage: http://www.marvell.com/multimedia-solutions/armada-1500-mini/
|
||||
88DE3006, Armada 1500 Mini Plus
|
||||
Design name: BG2CDP
|
||||
Core: Dual Core ARM Cortex-A7
|
||||
Homepage: http://www.marvell.com/multimedia-solutions/armada-1500-mini-plus/
|
||||
88DE3100, Armada 1500
|
||||
Design name: BG2
|
||||
Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
|
||||
Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
|
||||
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
|
||||
Product Brief: http://www.marvell.com/multimedia-solutions/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
|
||||
88DE3114, Armada 1500 Pro
|
||||
Design name: BG2-Q
|
||||
Design name: BG2Q
|
||||
Core: Quad Core ARM Cortex-A9, PL310 L2CC
|
||||
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
|
||||
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
|
||||
88DE????
|
||||
Design name: BG3
|
||||
Core: ARM Cortex-A15, CA15 integrated L2CC
|
||||
|
||||
Homepage: http://www.marvell.com/digital-entertainment/
|
||||
Homepage: http://www.marvell.com/multimedia-solutions/
|
||||
Directory: arch/arm/mach-berlin
|
||||
|
||||
Comments:
|
||||
|
||||
@ -49,7 +49,7 @@ to this new MFP mechanism, here are several key points:
|
||||
internal controllers like PWM, SSP and UART, with 128 internal signals
|
||||
which can be routed to external through one or more MFPs (e.g. GPIO<0>
|
||||
can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
|
||||
see arch/arm/mach-pxa/mach/include/mfp-pxa300.h)
|
||||
see arch/arm/mach-pxa/mfp-pxa300.h)
|
||||
|
||||
2. Alternate function configuration is removed from this GPIO controller,
|
||||
the remaining functions are pure GPIO-specific, i.e.
|
||||
@ -76,11 +76,11 @@ For board code writers, here are some guidelines:
|
||||
|
||||
1. include ONE of the following header files in your <board>.c:
|
||||
|
||||
- #include <mach/mfp-pxa25x.h>
|
||||
- #include <mach/mfp-pxa27x.h>
|
||||
- #include <mach/mfp-pxa300.h>
|
||||
- #include <mach/mfp-pxa320.h>
|
||||
- #include <mach/mfp-pxa930.h>
|
||||
- #include "mfp-pxa25x.h"
|
||||
- #include "mfp-pxa27x.h"
|
||||
- #include "mfp-pxa300.h"
|
||||
- #include "mfp-pxa320.h"
|
||||
- #include "mfp-pxa930.h"
|
||||
|
||||
NOTE: only one file in your <board>.c, depending on the processors used,
|
||||
because pin configuration definitions may conflict in these file (i.e.
|
||||
@ -203,20 +203,20 @@ make them effective there-after.
|
||||
1. Unified pin definitions - enum constants for all configurable pins
|
||||
2. processor-neutral bit definitions for a possible MFP configuration
|
||||
|
||||
- arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
|
||||
- arch/arm/mach-pxa/mfp-pxa3xx.h
|
||||
|
||||
for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
|
||||
configurations
|
||||
|
||||
- arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
|
||||
- arch/arm/mach-pxa/mfp-pxa2xx.h
|
||||
|
||||
for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations
|
||||
|
||||
- arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
|
||||
arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
|
||||
arch/arm/mach-pxa/include/mach/mfp-pxa300.h
|
||||
arch/arm/mach-pxa/include/mach/mfp-pxa320.h
|
||||
arch/arm/mach-pxa/include/mach/mfp-pxa930.h
|
||||
- arch/arm/mach-pxa/mfp-pxa25x.h
|
||||
arch/arm/mach-pxa/mfp-pxa27x.h
|
||||
arch/arm/mach-pxa/mfp-pxa300.h
|
||||
arch/arm/mach-pxa/mfp-pxa320.h
|
||||
arch/arm/mach-pxa/mfp-pxa930.h
|
||||
|
||||
for processor specific definitions
|
||||
|
||||
|
||||
@ -81,14 +81,13 @@ on higher end storage.
|
||||
|
||||
Default value for this parameter is 8ms.
|
||||
|
||||
latency
|
||||
-------
|
||||
This parameter is used to enable/disable the latency mode of the CFQ
|
||||
scheduler. If latency mode (called low_latency) is enabled, CFQ tries
|
||||
to recompute the slice time for each process based on the target_latency set
|
||||
for the system. This favors fairness over throughput. Disabling low
|
||||
latency (setting it to 0) ignores target latency, allowing each process in the
|
||||
system to get a full time slice.
|
||||
low_latency
|
||||
-----------
|
||||
This parameter is used to enable/disable the low latency mode of the CFQ
|
||||
scheduler. If enabled, CFQ tries to recompute the slice time for each process
|
||||
based on the target_latency set for the system. This favors fairness over
|
||||
throughput. Disabling low latency (setting it to 0) ignores target latency,
|
||||
allowing each process in the system to get a full time slice.
|
||||
|
||||
By default low latency mode is enabled.
|
||||
|
||||
|
||||
@ -819,6 +819,78 @@ PAGE_SIZE multiple when read back.
|
||||
the cgroup. This may not exactly match the number of
|
||||
processes killed but should generally be close.
|
||||
|
||||
memory.stat
|
||||
|
||||
A read-only flat-keyed file which exists on non-root cgroups.
|
||||
|
||||
This breaks down the cgroup's memory footprint into different
|
||||
types of memory, type-specific details, and other information
|
||||
on the state and past events of the memory management system.
|
||||
|
||||
All memory amounts are in bytes.
|
||||
|
||||
The entries are ordered to be human readable, and new entries
|
||||
can show up in the middle. Don't rely on items remaining in a
|
||||
fixed position; use the keys to look up specific values!
|
||||
|
||||
anon
|
||||
|
||||
Amount of memory used in anonymous mappings such as
|
||||
brk(), sbrk(), and mmap(MAP_ANONYMOUS)
|
||||
|
||||
file
|
||||
|
||||
Amount of memory used to cache filesystem data,
|
||||
including tmpfs and shared memory.
|
||||
|
||||
file_mapped
|
||||
|
||||
Amount of cached filesystem data mapped with mmap()
|
||||
|
||||
file_dirty
|
||||
|
||||
Amount of cached filesystem data that was modified but
|
||||
not yet written back to disk
|
||||
|
||||
file_writeback
|
||||
|
||||
Amount of cached filesystem data that was modified and
|
||||
is currently being written back to disk
|
||||
|
||||
inactive_anon
|
||||
active_anon
|
||||
inactive_file
|
||||
active_file
|
||||
unevictable
|
||||
|
||||
Amount of memory, swap-backed and filesystem-backed,
|
||||
on the internal memory management lists used by the
|
||||
page reclaim algorithm
|
||||
|
||||
pgfault
|
||||
|
||||
Total number of page faults incurred
|
||||
|
||||
pgmajfault
|
||||
|
||||
Number of major page faults incurred
|
||||
|
||||
memory.swap.current
|
||||
|
||||
A read-only single value file which exists on non-root
|
||||
cgroups.
|
||||
|
||||
The total amount of swap currently being used by the cgroup
|
||||
and its descendants.
|
||||
|
||||
memory.swap.max
|
||||
|
||||
A read-write single value file which exists on non-root
|
||||
cgroups. The default is "max".
|
||||
|
||||
Swap usage hard limit. If a cgroup's swap usage reaches this
|
||||
limit, anonymous meomry of the cgroup will not be swapped out.
|
||||
|
||||
|
||||
5-2-2. General Usage
|
||||
|
||||
@ -1291,3 +1363,20 @@ allocation from the slack available in other groups or the rest of the
|
||||
system than killing the group. Otherwise, memory.max is there to
|
||||
limit this type of spillover and ultimately contain buggy or even
|
||||
malicious applications.
|
||||
|
||||
The combined memory+swap accounting and limiting is replaced by real
|
||||
control over swap space.
|
||||
|
||||
The main argument for a combined memory+swap facility in the original
|
||||
cgroup design was that global or parental pressure would always be
|
||||
able to swap all anonymous memory of a child group, regardless of the
|
||||
child's own (possibly untrusted) configuration. However, untrusted
|
||||
groups can sabotage swapping by other means - such as referencing its
|
||||
anonymous memory in a tight loop - and an admin can not assume full
|
||||
swappability when overcommitting untrusted jobs.
|
||||
|
||||
For trusted jobs, on the other hand, a combined counter is not an
|
||||
intuitive userspace interface, and it flies in the face of the idea
|
||||
that cgroup controllers should account and limit specific physical
|
||||
resources. Swap space is a resource like all others in the system,
|
||||
and that's why unified hierarchy allows distributing it separately.
|
||||
|
||||
@ -150,7 +150,7 @@ an entry as shown below in the output.
|
||||
|
||||
If this is not mounted, do the following.
|
||||
|
||||
#mkdir /sysfs
|
||||
#mkdir /sys
|
||||
#mount -t sysfs sys /sys
|
||||
|
||||
Now you should see entries for all present cpu, the following is an example
|
||||
|
||||
@ -26,6 +26,10 @@ Raspberry Pi Model B+
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
|
||||
|
||||
Raspberry Pi 2 Model B
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
|
||||
|
||||
Raspberry Pi Compute Module
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
|
||||
|
||||
@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
bcm4708
|
||||
compatible = "brcm,bcm4708";
|
||||
|
||||
bcm4709
|
||||
compatible = "brcm,bcm4709";
|
||||
|
||||
bcm53012
|
||||
compatible = "brcm,bcm53012";
|
||||
|
||||
@ -0,0 +1,39 @@
|
||||
Broadcom Northstar Plus SoC CPU Enable Method
|
||||
---------------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPU in the following Broadcom SoCs:
|
||||
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the corresponding secondary "cpu" device tree node:
|
||||
- enable-method = "brcm,bcm-nsp-smp";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register which should hold the common
|
||||
entry point for a secondary CPU. This entry is cpu node specific
|
||||
and should be added per cpu. E.g., in case of NSP (BCM58625) which
|
||||
is a dual core CPU SoC, this entry should be added to cpu1 node.
|
||||
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
enable-method = "brcm,bcm-nsp-smp";
|
||||
secondary-boot-reg = <0xffff042c>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
25
Documentation/devicetree/bindings/arm/compulab-boards.txt
Normal file
25
Documentation/devicetree/bindings/arm/compulab-boards.txt
Normal file
@ -0,0 +1,25 @@
|
||||
CompuLab SB-SOM is a multi-module baseboard capable of carrying:
|
||||
- CM-T43
|
||||
- CM-T54
|
||||
- CM-QS600
|
||||
- CL-SOM-AM57x
|
||||
- CL-SOM-iMX7
|
||||
modules with minor modifications to the SB-SOM assembly.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = should be "compulab,sb-som"
|
||||
|
||||
Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
|
||||
Freescale i.MX7 ARM Cortex-A7 System-on-Chip.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "compulab,cl-som-imx7", "fsl,imx7d";
|
||||
|
||||
Compulab SBC-iMX7 is a single board computer based on the
|
||||
Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
|
||||
the CL-SOM-iMX7 System-on-Module providing most of the functions,
|
||||
and SB-SOM-iMX7 carrier board providing additional peripheral
|
||||
functions and connectors.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
|
||||
@ -191,6 +191,8 @@ nodes to be present and contain the properties described below.
|
||||
"allwinner,sun6i-a31"
|
||||
"allwinner,sun8i-a23"
|
||||
"arm,psci"
|
||||
"arm,realview-smp"
|
||||
"brcm,bcm-nsp-smp"
|
||||
"brcm,brahma-b15"
|
||||
"marvell,armada-375-smp"
|
||||
"marvell,armada-380-smp"
|
||||
@ -201,6 +203,7 @@ nodes to be present and contain the properties described below.
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,kpss-acc-v1"
|
||||
"qcom,kpss-acc-v2"
|
||||
"rockchip,rk3036-smp"
|
||||
"rockchip,rk3066-smp"
|
||||
"ste,dbx500-smp"
|
||||
|
||||
|
||||
@ -131,6 +131,10 @@ Example:
|
||||
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
|
||||
----------------------------------------------------------------
|
||||
|
||||
LS1043A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
|
||||
|
||||
LS2080A ARMv8 based Simulator model
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
|
||||
|
||||
@ -24,6 +24,8 @@ board. Currently known boards are:
|
||||
"buffalo,lswxl"
|
||||
"buffalo,lsxhl"
|
||||
"buffalo,lsxl"
|
||||
"cloudengines,pogo02"
|
||||
"cloudengines,pogoplugv4"
|
||||
"dlink,dns-320"
|
||||
"dlink,dns-320-a1"
|
||||
"dlink,dns-325"
|
||||
|
||||
@ -6,6 +6,7 @@ following property:
|
||||
Required root node property:
|
||||
|
||||
compatible: Must contain one of
|
||||
"mediatek,mt2701"
|
||||
"mediatek,mt6580"
|
||||
"mediatek,mt6589"
|
||||
"mediatek,mt6592"
|
||||
@ -17,6 +18,9 @@ compatible: Must contain one of
|
||||
|
||||
Supported boards:
|
||||
|
||||
- Evaluation board for MT2701:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
|
||||
- Evaluation board for MT6580:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
|
||||
|
||||
@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
Also it uses the common reset controller binding from
|
||||
Documentation/devicetree/bindings/reset/reset.txt.
|
||||
The available reset outputs are defined in
|
||||
dt-bindings/reset-controller/mt*-resets.h
|
||||
dt-bindings/reset/mt*-resets.h
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
Also it uses the common reset controller binding from
|
||||
Documentation/devicetree/bindings/reset/reset.txt.
|
||||
The available reset outputs are defined in
|
||||
dt-bindings/reset-controller/mt*-resets.h
|
||||
dt-bindings/reset/mt*-resets.h
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@ -138,9 +138,21 @@ Boards:
|
||||
- AM335X phyBOARD-WEGA: Single Board Computer dev kit
|
||||
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
|
||||
|
||||
- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4
|
||||
compatible = "compulab,cm-t335", "ti,am33xx"
|
||||
|
||||
- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
|
||||
compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
|
||||
|
||||
- OMAP5 EVM : Evaluation Module
|
||||
compatible = "ti,omap5-evm", "ti,omap5"
|
||||
|
||||
- AM437x CM-T43
|
||||
compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
|
||||
|
||||
- AM437x SBC-T43
|
||||
compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
|
||||
|
||||
- AM43x EPOS EVM
|
||||
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
@ -150,6 +162,12 @@ Boards:
|
||||
- AM437x SK EVM: AM437x StarterKit Evaluation Module
|
||||
compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
- AM57XX CL-SOM-AM57x
|
||||
compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- AM57XX SBC-AM57x
|
||||
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA742 EVM: Software Development Board for DRA742
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
|
||||
@ -1,6 +1,10 @@
|
||||
Rockchip platforms device tree bindings
|
||||
---------------------------------------
|
||||
|
||||
- Kylin RK3036 board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
|
||||
|
||||
- MarsBoard RK3066 board:
|
||||
Required root node properties:
|
||||
- compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
|
||||
@ -35,6 +39,11 @@ Rockchip platforms device tree bindings
|
||||
Required root node properties:
|
||||
- compatible = "netxeon,r89", "rockchip,rk3288";
|
||||
|
||||
- Google Brain (dev-board):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Jaq (Haier Chromebook 11 and more):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
|
||||
@ -49,6 +58,15 @@ Rockchip platforms device tree bindings
|
||||
"google,veyron-jerry-rev3", "google,veyron-jerry",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Mickey (Asus Chromebit CS10):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
|
||||
"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
|
||||
"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
|
||||
"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
|
||||
"google,veyron-mickey-rev0", "google,veyron-mickey",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Minnie (Asus Chromebook Flip C100P):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
|
||||
@ -69,6 +87,14 @@ Rockchip platforms device tree bindings
|
||||
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
|
||||
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Rockchip RK3368 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
|
||||
|
||||
- Rockchip R88 board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,r88", "rockchip,rk3368";
|
||||
|
||||
- Rockchip RK3228 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
|
||||
@ -47,6 +47,9 @@ Required properties:
|
||||
|
||||
- samsung,syscon-phandle Contains the PMU system controller node
|
||||
(To access the ADC_PHY register on Exynos5250/5420/5800/3250)
|
||||
Optional properties:
|
||||
- has-touchscreen: If present, indicates that a touchscreen is
|
||||
connected an usable.
|
||||
|
||||
Note: child nodes can be added for auto probing from device tree.
|
||||
|
||||
|
||||
@ -10,10 +10,13 @@ References:
|
||||
Revision r2p0
|
||||
- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
|
||||
Revision r0p1
|
||||
- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
|
||||
Manial Revision r2p0
|
||||
|
||||
- compatible : Should be:
|
||||
"arm,cortex-a9-scu"
|
||||
"arm,cortex-a5-scu"
|
||||
"arm,arm11mp-scu"
|
||||
|
||||
- reg : Specify the base address and the size of the SCU register window.
|
||||
|
||||
|
||||
@ -27,6 +27,8 @@ SoCs:
|
||||
compatible = "renesas,r8a7793"
|
||||
- R-Car E2 (R8A77940)
|
||||
compatible = "renesas,r8a7794"
|
||||
- R-Car H3 (R8A77950)
|
||||
compatible = "renesas,r8a7795"
|
||||
|
||||
|
||||
Boards:
|
||||
@ -57,5 +59,7 @@ Boards:
|
||||
compatible = "renesas,marzen", "renesas,r8a7779"
|
||||
- Porter (M2-LCDP)
|
||||
compatible = "renesas,porter", "renesas,r8a7791"
|
||||
- Salvator-X (RTP0RC7795SIPB0010S)
|
||||
compatible = "renesas,salvator-x", "renesas,r8a7795";
|
||||
- SILK (RTP0RC7794LCB00011S)
|
||||
compatible = "renesas,silk", "renesas,r8a7794"
|
||||
|
||||
6
Documentation/devicetree/bindings/arm/technologic.txt
Normal file
6
Documentation/devicetree/bindings/arm/technologic.txt
Normal file
@ -0,0 +1,6 @@
|
||||
Technologic Systems Platforms Device Tree Bindings
|
||||
--------------------------------------------------
|
||||
|
||||
TS-4800 board
|
||||
Required root node properties:
|
||||
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
|
||||
@ -0,0 +1,66 @@
|
||||
UniPhier System Bus
|
||||
|
||||
The UniPhier System Bus is an external bus that connects on-board devices to
|
||||
the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
|
||||
some control signals. It supports up to 8 banks (chip selects).
|
||||
|
||||
Before any access to the bus, the bus controller must be configured; the bus
|
||||
controller registers provide the control for the translation from the offset
|
||||
within each bank to the CPU-viewed address. The needed setup includes the base
|
||||
address, the size of each bank. Optionally, some timing parameters can be
|
||||
optimized for faster bus access.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "socionext,uniphier-system-bus".
|
||||
- reg: offset and length of the register set for the bus controller device.
|
||||
- #address-cells: should be 2. The first cell is the bank number (chip select).
|
||||
The second cell is the address offset within the bank.
|
||||
- #size-cells: should be 1.
|
||||
- ranges: should provide a proper address translation from the System Bus to
|
||||
the parent bus.
|
||||
|
||||
Note:
|
||||
The address region(s) that can be assigned for the System Bus is implementation
|
||||
defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
|
||||
while other SoCs can only use 0x40000000-0x4fffffff. There might be additional
|
||||
limitations depending on SoCs and the boot mode. The address translation is
|
||||
arbitrary as long as the banks are assigned in the supported address space with
|
||||
the required alignment and they do not overlap one another.
|
||||
For example, it is possible to map:
|
||||
bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
|
||||
It is also possible to map:
|
||||
bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
|
||||
There is no reason to stick to a particular translation mapping, but the
|
||||
"ranges" property should provide a "reasonable" default that is known to work.
|
||||
The software should initialize the bus controller according to it.
|
||||
|
||||
Example:
|
||||
|
||||
system-bus {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
reg = <0x58c00000 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0x00000000 0x42000000 0x02000000
|
||||
5 0x00000000 0x46000000 0x01000000>;
|
||||
|
||||
ethernet@1,01f00000 {
|
||||
compatible = "smsc,lan9115";
|
||||
reg = <1 0x01f00000 0x1000>;
|
||||
interrupts = <0 48 4>
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
uart@5,00200000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <5 0x00200000 0x20>;
|
||||
interrupts = <0 49 4>
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
};
|
||||
|
||||
In this example,
|
||||
- the Ethernet device is connected at the offset 0x01f00000 of CS1 and
|
||||
mapped to 0x43f00000 of the parent bus.
|
||||
- the UART device is connected at the offset 0x00200000 of CS5 and
|
||||
mapped to 0x46200000 of the parent bus.
|
||||
40
Documentation/devicetree/bindings/clock/arm-syscon-icst.txt
Normal file
40
Documentation/devicetree/bindings/clock/arm-syscon-icst.txt
Normal file
@ -0,0 +1,40 @@
|
||||
ARM System Controller ICST clocks
|
||||
|
||||
The ICS525 and ICS307 oscillators are produced by Integrated Devices
|
||||
Technology (IDT). ARM integrated these oscillators deeply into their
|
||||
reference designs by adding special control registers that manage such
|
||||
oscillators to their system controllers.
|
||||
|
||||
The ARM system controller contains logic to serialize and initialize
|
||||
an ICST clock request after a write to the 32 bit register at an offset
|
||||
into the system controller. Furthermore, to even be able to alter one of
|
||||
these frequencies, the system controller must first be unlocked by
|
||||
writing a special token to another offset in the system controller.
|
||||
|
||||
The ICST oscillator must be provided inside a system controller node.
|
||||
|
||||
Required properties:
|
||||
- lock-offset: the offset address into the system controller where the
|
||||
unlocking register is located
|
||||
- vco-offset: the offset address into the system controller where the
|
||||
ICST control register is located (even 32 bit address)
|
||||
- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307"
|
||||
- #clock-cells: must be <0>
|
||||
- clocks: parent clock, since the ICST needs a parent clock to derive its
|
||||
frequency from, this attribute is compulsory.
|
||||
|
||||
Example:
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
|
||||
oscclk0: osc0@0c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x0c>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
(...)
|
||||
};
|
||||
@ -0,0 +1,31 @@
|
||||
Broadcom BCM2835 auxiliary peripheral support
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
|
||||
area controlling clock gating to the peripherals, and providing an IRQ
|
||||
status register.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "brcm,bcm2835-aux"
|
||||
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
|
||||
found in include/dt-bindings/clock/bcm2835-aux.h
|
||||
- reg: Specifies base physical address and size of the registers
|
||||
- clocks: The parent clock phandle
|
||||
|
||||
Example:
|
||||
|
||||
clocks: cprman@7e101000 {
|
||||
compatible = "brcm,bcm2835-cprman";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x7e101000 0x2000>;
|
||||
clocks = <&clk_osc>;
|
||||
};
|
||||
|
||||
aux: aux@0x7e215004 {
|
||||
compatible = "brcm,bcm2835-aux";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x7e215000 0x8>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
};
|
||||
@ -208,3 +208,8 @@ These clock IDs are defined in:
|
||||
ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
|
||||
ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
|
||||
ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
|
||||
|
||||
BCM63138
|
||||
--------
|
||||
PLL and leaf clock compatible strings for BCM63138 are:
|
||||
"brcm,bcm63138-armpll"
|
||||
|
||||
22
Documentation/devicetree/bindings/clock/cs2000-cp.txt
Normal file
22
Documentation/devicetree/bindings/clock/cs2000-cp.txt
Normal file
@ -0,0 +1,22 @@
|
||||
CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "cirrus,cs2000-cp"
|
||||
- reg: The chip select number on the I2C bus
|
||||
- clocks: common clock binding for CLK_IN, XTI/REF_CLK
|
||||
- clock-names: CLK_IN : clk_in, XTI/REF_CLK : ref_clk
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Example:
|
||||
|
||||
&i2c2 {
|
||||
...
|
||||
cs2000: clk_multiplier@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&rcar_sound 0>, <&x12_clk>;
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,28 @@
|
||||
PLL divider based Dove clocks
|
||||
|
||||
Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
|
||||
high speed clocks for a number of peripherals. These dividers are part of
|
||||
the PMU, and thus this node should be a child of the PMU node.
|
||||
|
||||
The following clocks are provided:
|
||||
|
||||
ID Clock
|
||||
-------------
|
||||
0 AXI bus clock
|
||||
1 GPU clock
|
||||
2 VMeta clock
|
||||
3 LCD clock
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "marvell,dove-divider-clock"
|
||||
- reg : shall be the register address of the Core PLL and Clock Divider
|
||||
Control 0 register. This will cover that register, as well as the
|
||||
Core PLL and Clock Divider Control 1 register. Thus, it will have
|
||||
a size of 8.
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
divider_clk: core-clock@0064 {
|
||||
compatible = "marvell,dove-divider-clock";
|
||||
reg = <0x0064 0x8>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,56 @@
|
||||
NVIDIA Tegra210 Clock And Reset Controller
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||
for muxing and gating Tegra's clocks, and setting their rates.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra210-car"
|
||||
- reg : Should contain CAR registers location and length
|
||||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra210-car.h>.
|
||||
- #reset-cells : Should be 1.
|
||||
In clock consumers, this cell represents the bit number in the CAR's
|
||||
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra210-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car TEGRA210_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk_32k: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&tegra_car {
|
||||
clocks = <&clk_32k>;
|
||||
};
|
||||
};
|
||||
30
Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt
Normal file
30
Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt
Normal file
@ -0,0 +1,30 @@
|
||||
NXP LPC32xx Clock Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,lpc3220-clk"
|
||||
- reg: should contain clock controller registers location and length
|
||||
- #clock-cells: must be 1, the cell holds id of a clock provided by the
|
||||
clock controller
|
||||
- clocks: phandles of external oscillators, the list must contain one
|
||||
32768 Hz oscillator and may have one optional high frequency oscillator
|
||||
- clock-names: list of external oscillator clock names, must contain
|
||||
"xtal_32k" and may have optional "xtal"
|
||||
|
||||
Examples:
|
||||
|
||||
/* System Control Block */
|
||||
scb {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x040004000 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clk: clock-controller@0 {
|
||||
compatible = "nxp,lpc3220-clk";
|
||||
reg = <0x00 0x114>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtal_32k>, <&xtal>;
|
||||
clock-names = "xtal_32k", "xtal";
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,22 @@
|
||||
NXP LPC32xx USB Clock Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,lpc3220-usb-clk"
|
||||
- reg: should contain clock controller registers location and length
|
||||
- #clock-cells: must be 1, the cell holds id of a clock provided by the
|
||||
USB clock controller
|
||||
|
||||
Examples:
|
||||
|
||||
usb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x31020000 0x00001000>;
|
||||
|
||||
usbclk: clock-controller@f00 {
|
||||
compatible = "nxp,lpc3220-usb-clk";
|
||||
reg = <0xf00 0x100>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
@ -13,6 +13,7 @@ Required properties :
|
||||
"qcom,gcc-msm8974"
|
||||
"qcom,gcc-msm8974pro"
|
||||
"qcom,gcc-msm8974pro-ac"
|
||||
"qcom,gcc-msm8996"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
@ -9,6 +9,7 @@ Required properties :
|
||||
"qcom,mmcc-msm8660"
|
||||
"qcom,mmcc-msm8960"
|
||||
"qcom,mmcc-msm8974"
|
||||
"qcom,mmcc-msm8996"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
@ -20,6 +20,10 @@ Required Properties:
|
||||
clocks must be specified. For clocks with multiple parents, invalid
|
||||
settings must be specified as "<0>".
|
||||
- #clock-cells: Must be 0
|
||||
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- clock-output-names: The name of the clock as a free-form string
|
||||
|
||||
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,sh73a0-h8300-div-clock"
|
||||
- compatible: Must be "renesas,h8300-div-clock"
|
||||
|
||||
- clocks: Reference to the parent clocks ("extal1" and "extal2")
|
||||
|
||||
|
||||
@ -0,0 +1,56 @@
|
||||
* Rockchip RK3036 Clock and Reset Unit
|
||||
|
||||
The RK3036 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3036-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@20060000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20060000 0x100>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -0,0 +1,58 @@
|
||||
* Rockchip RK3228 Clock and Reset Unit
|
||||
|
||||
The RK3228 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3228-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10110000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10110000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -27,7 +27,9 @@ Required properties:
|
||||
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
|
||||
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
|
||||
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
|
||||
"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
|
||||
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
|
||||
"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
|
||||
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
|
||||
@ -55,6 +57,9 @@ Required properties:
|
||||
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
|
||||
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
|
||||
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
|
||||
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
|
||||
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
|
||||
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
|
||||
@ -68,8 +73,10 @@ Required properties:
|
||||
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
|
||||
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
|
||||
"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
|
||||
"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
|
||||
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
|
||||
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
|
||||
"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
@ -89,6 +96,9 @@ Required properties for all clocks:
|
||||
And "allwinner,*-usb-clk" clocks also require:
|
||||
- reset-cells : shall be set to 1
|
||||
|
||||
The "allwinner,sun4i-a10-ve-clk" clock also requires:
|
||||
- reset-cells : shall be set to 0
|
||||
|
||||
The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
|
||||
- #reset-cells : shall be set to 1
|
||||
- resets : shall be the reset control phandle for the mmc block.
|
||||
|
||||
23
Documentation/devicetree/bindings/clock/tango4-clock.txt
Normal file
23
Documentation/devicetree/bindings/clock/tango4-clock.txt
Normal file
@ -0,0 +1,23 @@
|
||||
* Sigma Designs Tango4 Clock Generator
|
||||
|
||||
The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
|
||||
for RAM and various peripheral devices). The clock binding described here
|
||||
is applicable to all Tango4 SoCs.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "sigma,tango4-clkgen".
|
||||
- reg: physical base address of the device and length of memory mapped region.
|
||||
- clocks: phandle of the input clock (crystal oscillator).
|
||||
- clock-output-names: should be "cpuclk" and "sysclk".
|
||||
- #clock-cells: should be set to 1.
|
||||
|
||||
Example:
|
||||
|
||||
clkgen: clkgen@10000 {
|
||||
compatible = "sigma,tango4-clkgen";
|
||||
reg = <0x10000 0x40>;
|
||||
clocks = <&xtal>;
|
||||
clock-output-names = "cpuclk", "sysclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,54 @@
|
||||
Etnaviv DRM master device
|
||||
=========================
|
||||
|
||||
The Etnaviv DRM master device is a virtual device needed to list all
|
||||
Vivante GPU cores that comprise the GPU subsystem.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
"fsl,imx-gpu-subsystem"
|
||||
"marvell,dove-gpu-subsystem"
|
||||
- cores: Should contain a list of phandles pointing to Vivante GPU devices
|
||||
|
||||
example:
|
||||
|
||||
gpu-subsystem {
|
||||
compatible = "fsl,imx-gpu-subsystem";
|
||||
cores = <&gpu_2d>, <&gpu_3d>;
|
||||
};
|
||||
|
||||
|
||||
Vivante GPU core devices
|
||||
========================
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "vivante,gc"
|
||||
A more specific compatible is not needed, as the cores contain chip
|
||||
identification registers at fixed locations, which provide all the
|
||||
necessary information to the driver.
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain the cores interrupt line
|
||||
- clocks: should contain one clock for entry in clock-names
|
||||
see Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
- clock-names:
|
||||
- "bus": AXI/register clock
|
||||
- "core": GPU core clock
|
||||
- "shader": Shader clock (only required if GPU has feature PIPE_3D)
|
||||
|
||||
Optional properties:
|
||||
- power-domains: a power domain consumer specifier according to
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
|
||||
example:
|
||||
|
||||
gpu_3d: gpu@00130000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x00130000 0x4000>;
|
||||
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
|
||||
<&clks IMX6QDL_CLK_GPU3D_CORE>,
|
||||
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
|
||||
clock-names = "bus", "core", "shader";
|
||||
power-domains = <&gpc 1>;
|
||||
};
|
||||
@ -1,3 +1,20 @@
|
||||
Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
|
||||
|
||||
DisplayPort is industry standard to accommodate the growing board adoption
|
||||
of digital display technology within the PC and CE industries.
|
||||
It consolidates the internal and external connection methods to reduce device
|
||||
complexity and cost. It also supports necessary features for important cross
|
||||
industry applications and provides performance scalability to enable the next
|
||||
generation of displays that feature higher color depths, refresh rates, and
|
||||
display resolutions.
|
||||
|
||||
eDP (embedded display port) device is compliant with Embedded DisplayPort
|
||||
standard as follows,
|
||||
- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
|
||||
- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
|
||||
|
||||
eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
|
||||
|
||||
The Exynos display port interface should be configured based on
|
||||
the type of panel connected to it.
|
||||
|
||||
@ -66,8 +83,15 @@ Optional properties for dp-controller:
|
||||
Hotplug detect GPIO.
|
||||
Indicates which GPIO should be used for hotplug
|
||||
detection
|
||||
-video interfaces: Device node can contain video interface port
|
||||
nodes according to [1].
|
||||
Video interfaces:
|
||||
Device node can contain video interface port nodes according to [1].
|
||||
The following are properties specific to those nodes:
|
||||
|
||||
endpoint node connected to bridge or panel node:
|
||||
- remote-endpoint: specifies the endpoint in panel or bridge node.
|
||||
This node is required in all kinds of exynos dp
|
||||
to represent the connection between dp and bridge
|
||||
or dp and panel.
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
@ -111,9 +135,18 @@ Board Specific portion:
|
||||
};
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
port {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&bridge_in>;
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
...
|
||||
port {
|
||||
dp_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -2,10 +2,9 @@ Device-Tree bindings for drm hdmi driver
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be one among the following:
|
||||
1) "samsung,exynos5-hdmi" <DEPRECATED>
|
||||
2) "samsung,exynos4210-hdmi"
|
||||
3) "samsung,exynos4212-hdmi"
|
||||
4) "samsung,exynos5420-hdmi"
|
||||
1) "samsung,exynos4210-hdmi"
|
||||
2) "samsung,exynos4212-hdmi"
|
||||
3) "samsung,exynos5420-hdmi"
|
||||
- reg: physical base address of the hdmi and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
||||
@ -14,17 +14,20 @@ Required properties:
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
* "bus_clk"
|
||||
* "byte_clk"
|
||||
* "core_clk"
|
||||
* "core_mmss_clk"
|
||||
* "iface_clk"
|
||||
* "mdp_core_clk"
|
||||
* "iface_clk"
|
||||
* "bus_clk"
|
||||
* "core_mmss_clk"
|
||||
* "byte_clk"
|
||||
* "pixel_clk"
|
||||
* "core_clk"
|
||||
For DSIv2, we need an additional clock:
|
||||
* "src_clk"
|
||||
- vdd-supply: phandle to vdd regulator device node
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vdda-supply: phandle to vdda regulator device node
|
||||
- qcom,dsi-phy: phandle to DSI PHY device node
|
||||
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
|
||||
|
||||
Optional properties:
|
||||
- panel@0: Node of panel connected to this DSI controller.
|
||||
@ -51,6 +54,7 @@ Required properties:
|
||||
* "qcom,dsi-phy-28nm-hpm"
|
||||
* "qcom,dsi-phy-28nm-lp"
|
||||
* "qcom,dsi-phy-20nm"
|
||||
* "qcom,dsi-phy-28nm-8960"
|
||||
- reg: Physical base address and length of the registers of PLL, PHY and PHY
|
||||
regulator
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
|
||||
@ -2,18 +2,28 @@ Qualcomm adreno/snapdragon display controller
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp" - mdp4
|
||||
* "qcom,mdp4" - mdp4
|
||||
* "qcom,mdp5" - mdp5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- connectors: array of phandles for output device(s)
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "src_clk"
|
||||
* "hdmi_clk"
|
||||
* "mpd_clk"
|
||||
- clock-names: the following clocks are required.
|
||||
For MDP4:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "lut_clk"
|
||||
* "src_clk"
|
||||
* "hdmi_clk"
|
||||
* "mdp_clk"
|
||||
For MDP5:
|
||||
* "bus_clk"
|
||||
* "iface_clk"
|
||||
* "core_clk_src"
|
||||
* "core_clk"
|
||||
* "lut_clk" (some MDP5 versions may not need this)
|
||||
* "vsync_clk"
|
||||
|
||||
Optional properties:
|
||||
- gpus: phandle for gpu device
|
||||
@ -26,7 +36,7 @@ Example:
|
||||
...
|
||||
|
||||
mdp: qcom,mdp@5100000 {
|
||||
compatible = "qcom,mdp";
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
connectors = <&hdmi>;
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
Boe Corporation 8.0" WUXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "boe,tv080wum-nl0"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@ -0,0 +1,7 @@
|
||||
Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "innolux,g121x1-l03"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@ -0,0 +1,7 @@
|
||||
Kyocera Corporation 12.1" XGA (1024x768) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "kyo,tcg121xglp"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@ -0,0 +1,20 @@
|
||||
Panasonic 10" WUXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "panasonic,vvx10f034n00"
|
||||
- reg: DSI virtual channel of the peripheral
|
||||
- power-supply: phandle of the regulator that provides the supply voltage
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Example:
|
||||
|
||||
mdss_dsi@fd922800 {
|
||||
panel@0 {
|
||||
compatible = "panasonic,vvx10f034n00";
|
||||
reg = <0>;
|
||||
power-supply = <&vreg_vsp>;
|
||||
backlight = <&lp8566_wled>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,7 @@
|
||||
QiaoDian XianShi Corporation 4"3 TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "qiaodian,qd43003c0-40"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@ -0,0 +1,22 @@
|
||||
Sharp Microelectronics 4.3" qHD TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,ls043t1le01-qhd"
|
||||
- reg: DSI virtual channel of the peripheral
|
||||
- power-supply: phandle of the regulator that provides the supply voltage
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
- reset-gpios: a GPIO spec for the reset pin
|
||||
|
||||
Example:
|
||||
|
||||
mdss_dsi@fd922800 {
|
||||
panel@0 {
|
||||
compatible = "sharp,ls043t1le01-qhd";
|
||||
reg = <0>;
|
||||
avdd-supply = <&pm8941_l22>;
|
||||
backlight = <&pm8941_wled>;
|
||||
reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,4 @@
|
||||
Startek Electronic Technology Co. KD050C 5.0" WVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "startek,startek-kd050c"
|
||||
@ -0,0 +1,60 @@
|
||||
Rockchip specific extensions to the Synopsys Designware MIPI DSI
|
||||
================================
|
||||
|
||||
Required properties:
|
||||
- #address-cells: Should be <1>.
|
||||
- #size-cells: Should be <0>.
|
||||
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
|
||||
- reg: Represent the physical address range of the controller.
|
||||
- interrupts: Represent the controller's interrupt to the CPU(s).
|
||||
- clocks, clock-names: Phandles to the controller's pll reference
|
||||
clock(ref) and APB clock(pclk), as described in [1].
|
||||
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
|
||||
- ports: contain a port node with endpoint definitions as defined in [2].
|
||||
For vopb,set the reg = <0> and set the reg = <1> for vopl.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
mipi_dsi: mipi@ff960000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
|
||||
reg = <0xff960000 0x4000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
|
||||
clock-names = "ref", "pclk";
|
||||
rockchip,grf = <&grf>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
mipi_in: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mipi_in_vopb: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vopb_out_mipi>;
|
||||
};
|
||||
mipi_in_vopl: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vopl_out_mipi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible ="boe,tv080wum-nl0";
|
||||
reg = <0>;
|
||||
|
||||
enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_en>;
|
||||
backlight = <&backlight>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
@ -7,6 +7,7 @@ buffer to an external LCD interface.
|
||||
Required properties:
|
||||
- compatible: value should be one of the following
|
||||
"rockchip,rk3288-vop";
|
||||
"rockchip,rk3036-vop";
|
||||
|
||||
- interrupts: should contain a list of all VOP IP block interrupts in the
|
||||
order: VSYNC, LCD_SYSTEM. The interrupt specifier
|
||||
|
||||
@ -47,10 +47,14 @@ Required properties:
|
||||
- a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r).
|
||||
|
||||
Optional properties:
|
||||
- clocks : List of clocks used by the framebuffer. Clocks listed here
|
||||
are expected to already be configured correctly. The OS must
|
||||
ensure these clocks are not modified or disabled while the
|
||||
simple framebuffer remains active.
|
||||
- clocks : List of clocks used by the framebuffer.
|
||||
- *-supply : Any number of regulators used by the framebuffer. These should
|
||||
be named according to the names in the device's design.
|
||||
|
||||
The above resources are expected to already be configured correctly.
|
||||
The OS must ensure they are not modified or disabled while the simple
|
||||
framebuffer remains active.
|
||||
|
||||
- display : phandle pointing to the primary display hardware node
|
||||
|
||||
Example:
|
||||
@ -68,6 +72,7 @@ chosen {
|
||||
stride = <(1600 * 2)>;
|
||||
format = "r5g6b5";
|
||||
clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>;
|
||||
lcd-supply = <®_dc1sw>;
|
||||
display = <&lcdc0>;
|
||||
};
|
||||
stdout-path = "display0";
|
||||
|
||||
@ -14,7 +14,14 @@ not described in these device tree bindings.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: must contain "renesas,rcar-dmac"
|
||||
- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,dmac-r8a7790" (R-Car H2)
|
||||
- "renesas,dmac-r8a7791" (R-Car M2-W)
|
||||
- "renesas,dmac-r8a7792" (R-Car V2H)
|
||||
- "renesas,dmac-r8a7793" (R-Car M2-N)
|
||||
- "renesas,dmac-r8a7794" (R-Car E2)
|
||||
- "renesas,dmac-r8a7795" (R-Car H3)
|
||||
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
|
||||
@ -35,7 +42,7 @@ Required Properties:
|
||||
Example: R8A7790 (R-Car H2) SYS-DMACs
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x20000>;
|
||||
interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
|
||||
0 200 IRQ_TYPE_LEVEL_HIGH
|
||||
@ -65,7 +72,7 @@ Example: R8A7790 (R-Car H2) SYS-DMACs
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e6720000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
|
||||
reg = <0 0xe6720000 0 0x20000>;
|
||||
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
|
||||
0 216 IRQ_TYPE_LEVEL_HIGH
|
||||
|
||||
@ -25,6 +25,7 @@ Required properties:
|
||||
ti,tca6416
|
||||
ti,tca6424
|
||||
ti,tca9539
|
||||
onsemi,pca9654
|
||||
exar,xra1202
|
||||
|
||||
Example:
|
||||
|
||||
@ -5,7 +5,8 @@ Required properties:
|
||||
|
||||
- compatible: should be "semtech,sx1506q",
|
||||
"semtech,sx1508q",
|
||||
"semtech,sx1509q".
|
||||
"semtech,sx1509q",
|
||||
"semtech,sx1502q".
|
||||
|
||||
- reg: The I2C slave address for this device.
|
||||
|
||||
|
||||
16
Documentation/devicetree/bindings/gpio/gpio-tps65086.txt
Normal file
16
Documentation/devicetree/bindings/gpio/gpio-tps65086.txt
Normal file
@ -0,0 +1,16 @@
|
||||
* TPS65086 GPO Controller bindings
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,tps65086-gpio".
|
||||
- gpio-controller : Marks the device node as a GPIO Controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number
|
||||
and the second cell is used to specify flags.
|
||||
See ../gpio/gpio.txt for possible values.
|
||||
|
||||
Example:
|
||||
|
||||
gpio4: gpio {
|
||||
compatible = "ti,tps65086-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
@ -6,6 +6,7 @@ Required properties:
|
||||
Optional properties:
|
||||
- autorepeat: Boolean, Enable auto repeat feature of Linux input
|
||||
subsystem.
|
||||
- label: String, name of the input device.
|
||||
|
||||
Each button (key) is represented as a sub-node of "gpio-keys":
|
||||
Subnode properties:
|
||||
|
||||
@ -14,6 +14,7 @@ Required properties:
|
||||
"mediatek,mt6582-sysirq"
|
||||
"mediatek,mt6580-sysirq"
|
||||
"mediatek,mt6577-sysirq"
|
||||
"mediatek,mt2701-sysirq"
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Use the same format as specified by GIC in
|
||||
Documentation/devicetree/bindings/arm/gic.txt
|
||||
|
||||
@ -0,0 +1,67 @@
|
||||
Microchip PIC32 Interrupt Controller
|
||||
====================================
|
||||
|
||||
The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
|
||||
It handles all internal and external interrupts. This controller exists outside
|
||||
of the CPU and is the arbitrator of all interrupts (including interrupts from
|
||||
the CPU itself) before they are presented to the CPU.
|
||||
|
||||
External interrupts have a software configurable edge polarity. Non external
|
||||
interrupts have a type and polarity that is determined by the source of the
|
||||
interrupt.
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
- compatible: Should be "microchip,pic32mzda-evic"
|
||||
- reg: Specifies physical base address and size of register range.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt cells: Specifies the number of cells used to encode an interrupt
|
||||
source connected to this controller. The value shall be 2 and interrupt
|
||||
descriptor shall have the following format:
|
||||
|
||||
<hw_irq irq_type>
|
||||
|
||||
hw_irq - represents the hardware interrupt number as in the data sheet.
|
||||
irq_type - is used to describe the type and polarity of an interrupt. For
|
||||
internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
|
||||
IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
|
||||
IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
- microchip,external-irqs: u32 array of external interrupts with software
|
||||
polarity configuration. This array corresponds to the bits in the INTCON
|
||||
SFR.
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
evic: interrupt-controller@1f810000 {
|
||||
compatible = "microchip,pic32mzda-evic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1f810000 0x1000>;
|
||||
microchip,external-irqs = <3 8 13 18 23>;
|
||||
};
|
||||
|
||||
Each device/peripheral must request its interrupt line with the associated type
|
||||
and polarity.
|
||||
|
||||
Internal interrupt DTS snippet
|
||||
------------------------------
|
||||
|
||||
device@1f800000 {
|
||||
...
|
||||
interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
...
|
||||
};
|
||||
|
||||
External interrupt DTS snippet
|
||||
------------------------------
|
||||
|
||||
device@1f800000 {
|
||||
...
|
||||
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
||||
...
|
||||
};
|
||||
@ -7,7 +7,15 @@ connected to the IPMMU through a port called micro-TLB.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must contain "renesas,ipmmu-vmsa".
|
||||
- compatible: Must contain SoC-specific and generic entries from below.
|
||||
|
||||
- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
|
||||
- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
|
||||
- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
|
||||
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
|
||||
- "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
|
||||
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
|
||||
|
||||
- reg: Base address and size of the IPMMU registers.
|
||||
- interrupts: Specifiers for the MMU fault interrupts. For instances that
|
||||
support secure mode two interrupts must be specified, for non-secure and
|
||||
@ -27,7 +35,7 @@ node with the following property:
|
||||
Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
|
||||
|
||||
ipmmu_mx: mmu@fe951000 {
|
||||
compatible = "renasas,ipmmu-vmsa";
|
||||
compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
|
||||
reg = <0 0xfe951000 0 0x1000>;
|
||||
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -7,6 +7,10 @@ Required properties:
|
||||
- reg: should contain G-Scaler physical address location and length.
|
||||
- interrupts: should contain G-Scaler interrupt number
|
||||
|
||||
Optional properties:
|
||||
- samsung,sysreg: handle to syscon used to control the system registers to
|
||||
set writeback input and destination
|
||||
|
||||
Example:
|
||||
|
||||
gsc_0: gsc@0x13e00000 {
|
||||
|
||||
@ -0,0 +1,31 @@
|
||||
* Microchip PIC32MZDA Platforms
|
||||
|
||||
PIC32MZDA Starter Kit
|
||||
Required root node properties:
|
||||
- compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"
|
||||
|
||||
CPU nodes:
|
||||
----------
|
||||
A "cpus" node is required. Required properties:
|
||||
- #address-cells: Must be 1.
|
||||
- #size-cells: Must be 0.
|
||||
A CPU sub-node is also required. Required properties:
|
||||
- device_type: Must be "cpu".
|
||||
- compatible: Must be "mti,mips14KEc".
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mti,mips14KEc";
|
||||
};
|
||||
};
|
||||
|
||||
Boot protocol
|
||||
--------------
|
||||
In accordance with Unified Hosting Interface Reference Manual (MD01069), the
|
||||
bootloader must pass the following arguments to the kernel:
|
||||
- $a0: -2.
|
||||
- $a1: KSEG0 address of the flattened device-tree blob.
|
||||
@ -68,7 +68,7 @@ ethernet@f0b60000 {
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <1000>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,28nm-gphy", "ethernet-phy-ieee802.3-c22";
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -115,7 +115,7 @@ ethernet@f0ba0000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
max-speed = <1000>;
|
||||
reg = <0x0>;
|
||||
compatible = "brcm,bcm53125", "ethernet-phy-ieee802.3-c22";
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -4,8 +4,6 @@ Required properties:
|
||||
- compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
|
||||
"hisilicon,hns-dsaf-v1" is for hip05.
|
||||
"hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
|
||||
- dsa-name: dsa fabric name who provide this interface.
|
||||
should be "dsafX", X is the dsaf id.
|
||||
- mode: dsa fabric mode string. only support one of dsaf modes like these:
|
||||
"2port-64vf",
|
||||
"6port-16rss",
|
||||
@ -26,9 +24,8 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
dsa: dsa@c7000000 {
|
||||
dsaf0: dsa@c7000000 {
|
||||
compatible = "hisilicon,hns-dsaf-v1";
|
||||
dsa_name = "dsaf0";
|
||||
mode = "6port-16rss";
|
||||
interrupt-parent = <&mbigen_dsa>;
|
||||
reg = <0x0 0xC0000000 0x0 0x420000
|
||||
|
||||
@ -4,8 +4,9 @@ Required properties:
|
||||
- compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
|
||||
"hisilicon,hns-nic-v1" is for hip05.
|
||||
"hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
|
||||
- ae-name: accelerator name who provides this interface,
|
||||
is simply a name referring to the name of name in the accelerator node.
|
||||
- ae-handle: accelerator engine handle for hns,
|
||||
specifies a reference to the associating hardware driver node.
|
||||
see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
|
||||
- port-id: is the index of port provided by DSAF (the accelerator). DSAF can
|
||||
connect to 8 PHYs. Port 0 to 1 are both used for adminstration purpose. They
|
||||
are called debug ports.
|
||||
@ -41,7 +42,7 @@ Example:
|
||||
|
||||
ethernet@0{
|
||||
compatible = "hisilicon,hns-nic-v1";
|
||||
ae-name = "dsaf0";
|
||||
ae-handle = <&dsaf0>;
|
||||
port-id = <0>;
|
||||
local-mac-address = [a2 14 e4 4b 56 76];
|
||||
};
|
||||
|
||||
@ -6,12 +6,17 @@ Required properties:
|
||||
- interrupts: interrupt for the device
|
||||
- phy: See ethernet.txt file in the same directory.
|
||||
- phy-mode: See ethernet.txt file in the same directory
|
||||
- clocks: a pointer to the reference clock for this device.
|
||||
- clocks: List of clocks for this device. At least one clock is
|
||||
mandatory for the core clock. If several clocks are given, then the
|
||||
clock-names property must be used to identify them.
|
||||
|
||||
Optional properties:
|
||||
- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
|
||||
Value is presented in bytes. If not used, by default 1600B is set for
|
||||
"marvell,armada-370-neta" and 9800B for others.
|
||||
- clock-names: List of names corresponding to clocks property; shall be
|
||||
"core" for core clock and "bus" for the optional bus clock.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@ -38,7 +38,6 @@ Example :
|
||||
|
||||
phy11: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -48,7 +47,6 @@ Example :
|
||||
};
|
||||
phy12: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -58,7 +56,6 @@ Example :
|
||||
};
|
||||
phy13: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -68,7 +65,6 @@ Example :
|
||||
};
|
||||
phy14: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -85,7 +81,6 @@ Example :
|
||||
|
||||
phy21: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -95,7 +90,6 @@ Example :
|
||||
};
|
||||
phy22: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -105,7 +99,6 @@ Example :
|
||||
};
|
||||
phy23: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -115,7 +108,6 @@ Example :
|
||||
};
|
||||
phy24: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
|
||||
@ -47,7 +47,6 @@ Example :
|
||||
|
||||
phy11: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -57,7 +56,6 @@ Example :
|
||||
};
|
||||
phy12: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -67,7 +65,6 @@ Example :
|
||||
};
|
||||
phy13: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -77,7 +74,6 @@ Example :
|
||||
};
|
||||
phy14: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -94,7 +90,6 @@ Example :
|
||||
|
||||
phy21: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -104,7 +99,6 @@ Example :
|
||||
};
|
||||
phy22: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -114,7 +108,6 @@ Example :
|
||||
};
|
||||
phy23: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
@ -124,7 +117,6 @@ Example :
|
||||
};
|
||||
phy24: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "marvell,88e1149r";
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
|
||||
@ -0,0 +1,26 @@
|
||||
Mediatek Gigabit Switch
|
||||
=======================
|
||||
|
||||
The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621).
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupt-parent: Should be the phandle for the interrupt controller
|
||||
that services interrupts for this device
|
||||
- interrupts: Should contain the gigabit switches interrupt
|
||||
- resets: Should contain the gigabit switches resets
|
||||
- reset-names: Should contain the reset names "gsw"
|
||||
|
||||
Example:
|
||||
|
||||
gsw@10110000 {
|
||||
compatible = "ralink,mt7620-gsw";
|
||||
reg = <0x10110000 8000>;
|
||||
|
||||
resets = <&rstctrl 23>;
|
||||
reset-names = "gsw";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
@ -17,8 +17,7 @@ Optional Properties:
|
||||
"ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
|
||||
PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
|
||||
specifications. If neither of these are specified, the default is to
|
||||
assume clause 22. The compatible list may also contain other
|
||||
elements.
|
||||
assume clause 22.
|
||||
|
||||
If the phy's identifier is known then the list may contain an entry
|
||||
of the form: "ethernet-phy-idAAAA.BBBB" where
|
||||
@ -28,6 +27,9 @@ Optional Properties:
|
||||
4 hex digits. This is the chip vendor OUI bits 19:24,
|
||||
followed by 10 bits of a vendor specific ID.
|
||||
|
||||
The compatible list should not contain other values than those
|
||||
listed here.
|
||||
|
||||
- max-speed: Maximum PHY supported speed (10, 100, 1000...)
|
||||
|
||||
- broken-turn-around: If set, indicates the PHY device does not correctly
|
||||
|
||||
61
Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
Normal file
61
Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
Normal file
@ -0,0 +1,61 @@
|
||||
Ralink Frame Engine Ethernet controller
|
||||
=======================================
|
||||
|
||||
The Ralink frame engine ethernet controller can be found on Ralink and
|
||||
Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
|
||||
|
||||
Depending on the SoC, there is a number of ports connected to the CPU port
|
||||
directly and/or via a (gigabit-)switch.
|
||||
|
||||
* Ethernet controller node
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
|
||||
"ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
|
||||
"mediatek,mt7620-eth", "mediatek,mt7621-eth"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupt-parent: Should be the phandle for the interrupt controller
|
||||
that services interrupts for this device
|
||||
- interrupts: Should contain the frame engines interrupt
|
||||
- resets: Should contain the frame engines resets
|
||||
- reset-names: Should contain the reset names "fe". If a switch is present
|
||||
"esw" is also required.
|
||||
|
||||
|
||||
* Ethernet port node
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "ralink,eth-port"
|
||||
- reg: The number of the physical port
|
||||
- phy-handle: reference to the node describing the phy
|
||||
|
||||
Example:
|
||||
|
||||
mdio-bus {
|
||||
...
|
||||
phy0: ethernet-phy@0 {
|
||||
phy-mode = "mii";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@400000 {
|
||||
compatible = "ralink,rt2880-eth";
|
||||
reg = <0x00400000 10000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
resets = <&rstctrl 18>;
|
||||
reset-names = "fe";
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <5>;
|
||||
|
||||
port@0 {
|
||||
compatible = "ralink,eth-port";
|
||||
reg = <0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
};
|
||||
32
Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
Normal file
32
Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
Normal file
@ -0,0 +1,32 @@
|
||||
Ralink Fast Ethernet Embedded Switch
|
||||
====================================
|
||||
|
||||
The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
|
||||
SoCs (RT3x5x, RT5350, MT76x8).
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "ralink,rt3050-esw"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupt-parent: Should be the phandle for the interrupt controller
|
||||
that services interrupts for this device
|
||||
- interrupts: Should contain the embedded switches interrupt
|
||||
- resets: Should contain the embedded switches resets
|
||||
- reset-names: Should contain the reset names "esw"
|
||||
|
||||
Optional properties:
|
||||
- ralink,portmap: can be used to choose if the default switch setup is
|
||||
llllw or wllll
|
||||
- ralink,led_polarity: override the active high/low settings of the leds
|
||||
|
||||
Example:
|
||||
|
||||
esw@10110000 {
|
||||
compatible = "ralink,rt3050-esw";
|
||||
reg = <0x10110000 8000>;
|
||||
|
||||
resets = <&rstctrl 23>;
|
||||
reset-names = "esw";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
@ -1,7 +1,10 @@
|
||||
* Broadcom iProc PCIe controller with the platform bus interface
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "brcm,iproc-pcie"
|
||||
- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
|
||||
for PAXC. PAXB-based root complex is used for external endpoint devices.
|
||||
PAXC-based root complex is connected to emulated endpoint devices
|
||||
internal to the ASIC
|
||||
- reg: base address and length of the PCIe controller I/O register space
|
||||
- #interrupt-cells: set to <1>
|
||||
- interrupt-map-mask and interrupt-map, standard PCI properties to define the
|
||||
@ -32,6 +35,28 @@ Optional:
|
||||
- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
|
||||
increase the outbound window size
|
||||
|
||||
MSI support (optional):
|
||||
|
||||
For older platforms without MSI integrated in the GIC, iProc PCIe core provides
|
||||
an event queue based MSI support. The iProc MSI uses host memories to store
|
||||
MSI posted writes in the event queues
|
||||
|
||||
- msi-parent: Link to the device node of the MSI controller. On newer iProc
|
||||
platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
|
||||
platforms without MSI support in its interrupt controller, one may use the
|
||||
event queue based MSI support integrated within the iProc PCIe core.
|
||||
|
||||
When the iProc event queue based MSI is used, one needs to define the
|
||||
following properties in the MSI device node:
|
||||
- compatible: Must be "brcm,iproc-msi"
|
||||
- msi-controller: claims itself as an MSI controller
|
||||
- interrupt-parent: Link to its parent interrupt device
|
||||
- interrupts: List of interrupt IDs from its parent interrupt device
|
||||
|
||||
Optional properties:
|
||||
- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
|
||||
require the interrupt enable registers to be set explicitly to enable MSI
|
||||
|
||||
Example:
|
||||
pcie0: pcie@18012000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
@ -58,6 +83,19 @@ Example:
|
||||
brcm,pcie-ob-oarr-size;
|
||||
brcm,pcie-ob-axi-offset = <0x00000000>;
|
||||
brcm,pcie-ob-window-size = <256>;
|
||||
|
||||
msi-parent = <&msi0>;
|
||||
|
||||
/* iProc event queue based MSI */
|
||||
msi0: msi@18012000 {
|
||||
compatible = "brcm,iproc-msi";
|
||||
msi-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 97 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 98 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 99 IRQ_TYPE_NONE>,
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@18013000 {
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
HiSilicon PCIe host bridge DT description
|
||||
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
|
||||
|
||||
HiSilicon PCIe host controller is based on Designware PCI core.
|
||||
It shares common functions with PCIe Designware core driver and inherits
|
||||
@ -7,8 +7,8 @@ Documentation/devicetree/bindings/pci/designware-pci.txt.
|
||||
|
||||
Additional properties are described here:
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "hisilicon,hip05-pcie".
|
||||
Required properties
|
||||
- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
|
||||
- reg: Should contain rc_dbi, config registers location and length.
|
||||
- reg-names: Must include the following entries:
|
||||
"rc_dbi": controller configuration registers;
|
||||
@ -20,7 +20,7 @@ Optional properties:
|
||||
- status: Either "ok" or "disabled".
|
||||
- dma-coherent: Present if DMA operations are coherent.
|
||||
|
||||
Example:
|
||||
Hip05 Example (note that Hip06 is the same except compatible):
|
||||
pcie@0xb0080000 {
|
||||
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
|
||||
reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
|
||||
|
||||
@ -8,7 +8,14 @@ OHCI and EHCI controllers.
|
||||
Required properties:
|
||||
- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
|
||||
"renesas,pci-r8a7791" for the R8A7791 SoC;
|
||||
"renesas,pci-r8a7794" for the R8A7794 SoC.
|
||||
"renesas,pci-r8a7794" for the R8A7794 SoC;
|
||||
"renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
|
||||
|
||||
|
||||
When compatible with the generic version, nodes must list the
|
||||
SoC-specific version corresponding to the platform first
|
||||
followed by the generic version.
|
||||
|
||||
- reg: A list of physical regions to access the device: the first is
|
||||
the operational registers for the OHCI/EHCI controllers and the
|
||||
second is for the bridge configuration and control registers.
|
||||
@ -24,10 +31,15 @@ Required properties:
|
||||
- interrupt-map-mask: standard property that helps to define the interrupt
|
||||
mapping.
|
||||
|
||||
Optional properties:
|
||||
- dma-ranges: a single range for the inbound memory region. If not supplied,
|
||||
defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
|
||||
allowed combinations of address and size.
|
||||
|
||||
Example SoC configuration:
|
||||
|
||||
pci0: pci@ee090000 {
|
||||
compatible = "renesas,pci-r8a7790";
|
||||
compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
reg = <0x0 0xee090000 0x0 0xc00>,
|
||||
<0x0 0xee080000 0x0 0x1100>;
|
||||
@ -38,6 +50,7 @@ Example SoC configuration:
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
|
||||
interrupt-map-mask = <0xff00 0 0 0x7>;
|
||||
interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
|
||||
0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
|
||||
|
||||
233
Documentation/devicetree/bindings/pci/qcom,pcie.txt
Normal file
233
Documentation/devicetree/bindings/pci/qcom,pcie.txt
Normal file
@ -0,0 +1,233 @@
|
||||
* Qualcomm PCI express root complex
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Value should contain
|
||||
- "qcom,pcie-ipq8064" for ipq8064
|
||||
- "qcom,pcie-apq8064" for apq8064
|
||||
- "qcom,pcie-apq8084" for apq8084
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Register ranges as listed in the reg-names property
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include the following entries
|
||||
- "parf" Qualcomm specific registers
|
||||
- "dbi" Designware PCIe registers
|
||||
- "elbi" External local bus interface registers
|
||||
- "config" PCIe configuration space
|
||||
|
||||
- device_type:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Should be "pci". As specified in designware-pcie.txt
|
||||
|
||||
- #address-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: Should be 3. As specified in designware-pcie.txt
|
||||
|
||||
- #size-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: Should be 2. As specified in designware-pcie.txt
|
||||
|
||||
- ranges:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: As specified in designware-pcie.txt
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: MSI interrupt
|
||||
|
||||
- interrupt-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Should contain "msi"
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: Should be 1. As specified in designware-pcie.txt
|
||||
|
||||
- interrupt-map-mask:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: As specified in designware-pcie.txt
|
||||
|
||||
- interrupt-map:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: As specified in designware-pcie.txt
|
||||
|
||||
- clocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: List of phandle and clock specifier pairs as listed
|
||||
in clock-names property
|
||||
|
||||
- clock-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Should contain the following entries
|
||||
- "iface" Configuration AHB clock
|
||||
|
||||
- clock-names:
|
||||
Usage: required for ipq/apq8064
|
||||
Value type: <stringlist>
|
||||
Definition: Should contain the following entries
|
||||
- "core" Clocks the pcie hw block
|
||||
- "phy" Clocks the pcie PHY block
|
||||
- clock-names:
|
||||
Usage: required for apq8084
|
||||
Value type: <stringlist>
|
||||
Definition: Should contain the following entries
|
||||
- "aux" Auxiliary (AUX) clock
|
||||
- "bus_master" Master AXI clock
|
||||
- "bus_slave" Slave AXI clock
|
||||
- resets:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: List of phandle and reset specifier pairs as listed
|
||||
in reset-names property
|
||||
|
||||
- reset-names:
|
||||
Usage: required for ipq/apq8064
|
||||
Value type: <stringlist>
|
||||
Definition: Should contain the following entries
|
||||
- "axi" AXI reset
|
||||
- "ahb" AHB reset
|
||||
- "por" POR reset
|
||||
- "pci" PCI reset
|
||||
- "phy" PHY reset
|
||||
|
||||
- reset-names:
|
||||
Usage: required for apq8084
|
||||
Value type: <stringlist>
|
||||
Definition: Should contain the following entries
|
||||
- "core" Core reset
|
||||
|
||||
- power-domains:
|
||||
Usage: required for apq8084
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A phandle and power domain specifier pair to the
|
||||
power domain which is responsible for collapsing
|
||||
and restoring power to the peripheral
|
||||
|
||||
- vdda-supply:
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: A phandle to the core analog power supply
|
||||
|
||||
- vdda_phy-supply:
|
||||
Usage: required for ipq/apq8064
|
||||
Value type: <phandle>
|
||||
Definition: A phandle to the analog power supply for PHY
|
||||
|
||||
- vdda_refclk-supply:
|
||||
Usage: required for ipq/apq8064
|
||||
Value type: <phandle>
|
||||
Definition: A phandle to the analog power supply for IC which generates
|
||||
reference clock
|
||||
|
||||
- phys:
|
||||
Usage: required for apq8084
|
||||
Value type: <phandle>
|
||||
Definition: List of phandle(s) as listed in phy-names property
|
||||
|
||||
- phy-names:
|
||||
Usage: required for apq8084
|
||||
Value type: <stringlist>
|
||||
Definition: Should contain "pciephy"
|
||||
|
||||
- <name>-gpios:
|
||||
Usage: optional
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: List of phandle and gpio specifier pairs. Should contain
|
||||
- "perst-gpios" PCIe endpoint reset signal line
|
||||
- "wake-gpios" PCIe endpoint wake signal line
|
||||
|
||||
* Example for ipq/apq8064
|
||||
pcie@1b500000 {
|
||||
compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
|
||||
reg = <0x1b500000 0x1000
|
||||
0x1b502000 0x80
|
||||
0x1b600000 0x100
|
||||
0x0ff00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
|
||||
0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
clocks = <&gcc PCIE_A_CLK>,
|
||||
<&gcc PCIE_H_CLK>,
|
||||
<&gcc PCIE_PHY_CLK>;
|
||||
clock-names = "core", "iface", "phy";
|
||||
resets = <&gcc PCIE_ACLK_RESET>,
|
||||
<&gcc PCIE_HCLK_RESET>,
|
||||
<&gcc PCIE_POR_RESET>,
|
||||
<&gcc PCIE_PCI_RESET>,
|
||||
<&gcc PCIE_PHY_RESET>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy";
|
||||
pinctrl-0 = <&pcie_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
* Example for apq8084
|
||||
pcie0@fc520000 {
|
||||
compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
|
||||
reg = <0xfc520000 0x2000>,
|
||||
<0xff000000 0x1000>,
|
||||
<0xff001000 0x1000>,
|
||||
<0xff002000 0x2000>;
|
||||
reg-names = "parf", "dbi", "elbi", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
|
||||
0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>;
|
||||
clock-names = "iface", "master_bus", "slave_bus", "aux";
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc PCIE0_GDSC>;
|
||||
vdda-supply = <&pma8084_l3>;
|
||||
phys = <&pciephy0>;
|
||||
phy-names = "pciephy";
|
||||
perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
@ -1,8 +1,16 @@
|
||||
* Renesas RCar PCIe interface
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain one of the following
|
||||
"renesas,pcie-r8a7779", "renesas,pcie-r8a7790", "renesas,pcie-r8a7791"
|
||||
compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
|
||||
"renesas,pcie-r8a7790" for the R8A7790 SoC;
|
||||
"renesas,pcie-r8a7791" for the R8A7791 SoC;
|
||||
"renesas,pcie-r8a7795" for the R8A7795 SoC;
|
||||
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
|
||||
|
||||
When compatible with the generic version, nodes must list the
|
||||
SoC-specific version corresponding to the platform first
|
||||
followed by the generic version.
|
||||
|
||||
- reg: base address and length of the pcie controller registers.
|
||||
- #address-cells: set to <3>
|
||||
- #size-cells: set to <2>
|
||||
@ -25,7 +33,7 @@ Example:
|
||||
SoC specific DT Entry:
|
||||
|
||||
pcie: pcie@fe000000 {
|
||||
compatible = "renesas,pcie-r8a7791";
|
||||
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
|
||||
reg = <0 0xfe000000 0 0x80000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
18
Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
Normal file
18
Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
Normal file
@ -0,0 +1,18 @@
|
||||
* Atheros AR71XX/9XXX USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: "qca,ar7100-usb-phy"
|
||||
- #phys-cells: should be 0
|
||||
- reset-names: "usb-phy"[, "usb-suspend-override"]
|
||||
- resets: references to the reset controllers
|
||||
|
||||
Example:
|
||||
|
||||
usb-phy {
|
||||
compatible = "qca,ar7100-usb-phy";
|
||||
|
||||
reset-names = "usb-phy", "usb-suspend-override";
|
||||
resets = <&rst 4>, <&rst 3>;
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
@ -6,7 +6,12 @@ Required properties:
|
||||
|
||||
Examples:
|
||||
|
||||
pwm@0x4005C000 {
|
||||
pwm@4005c000 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005C000 0x8>;
|
||||
reg = <0x4005c000 0x4>;
|
||||
};
|
||||
|
||||
pwm@4005c004 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005c004 0x4>;
|
||||
};
|
||||
|
||||
18
Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
Normal file
18
Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
Normal file
@ -0,0 +1,18 @@
|
||||
* OMAP PWM for dual-mode timers
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall contain "ti,omap-dmtimer-pwm".
|
||||
- ti,timers: phandle to PWM capable OMAP timer. See arm/omap/timer.txt for info
|
||||
about these timers.
|
||||
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
Optional properties:
|
||||
- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
|
||||
|
||||
Example:
|
||||
pwm9: dmtimer-pwm@9 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
ti,timers = <&timer9>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
@ -26,7 +26,11 @@ Example:
|
||||
ti,pmic-shutdown-controller;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: dcdc1 {
|
||||
reg = <0>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
@ -34,6 +38,7 @@ Example:
|
||||
};
|
||||
|
||||
dcdc2_reg: dcdc2 {
|
||||
reg = <1>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
@ -41,6 +46,7 @@ Example:
|
||||
};
|
||||
|
||||
dcdc3_reg: dcc3 {
|
||||
reg = <2>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
@ -48,6 +54,7 @@ Example:
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
reg = <3>;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
@ -55,6 +62,7 @@ Example:
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
reg = <4>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
@ -62,6 +70,7 @@ Example:
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
reg = <5>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
@ -69,6 +78,7 @@ Example:
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
reg = <6>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
||||
@ -0,0 +1,34 @@
|
||||
Hisilicon System Reset Controller
|
||||
======================================
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
The reset controller registers are part of the system-ctl block on
|
||||
hi6220 SoC.
|
||||
|
||||
Required properties:
|
||||
- compatible: may be "hisilicon,hi6220-sysctrl"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
Example:
|
||||
sys_ctrl: sys_ctrl@f7030000 {
|
||||
compatible = "hisilicon,hi6220-sysctrl", "syscon";
|
||||
reg = <0x0 0xf7030000 0x0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
example:
|
||||
|
||||
uart1: serial@..... {
|
||||
...
|
||||
resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
|
||||
...
|
||||
};
|
||||
|
||||
The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>.
|
||||
@ -2,15 +2,15 @@
|
||||
|
||||
Required properties:
|
||||
- compatible should contain:
|
||||
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
|
||||
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
|
||||
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
|
||||
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
|
||||
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
|
||||
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
|
||||
* "mediatek,mt2701-uart" for MT2701 compatible UARTS
|
||||
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
|
||||
* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795,
|
||||
MT6589, MT6582, MT6580, MT6577)
|
||||
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
|
||||
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
|
||||
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
|
||||
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
|
||||
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
|
||||
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
|
||||
* "mediatek,mt6577-uart" for MT6577 and all of the above
|
||||
|
||||
- reg: The base address of the UART register bank.
|
||||
|
||||
|
||||
@ -0,0 +1,47 @@
|
||||
Raspberry Pi power domain driver
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "raspberrypi,bcm2835-power".
|
||||
- firmware: Reference to the RPi firmware device node.
|
||||
- #power-domain-cells: Should be <1>, we providing multiple power domains.
|
||||
|
||||
The valid defines for power domain are:
|
||||
|
||||
RPI_POWER_DOMAIN_I2C0
|
||||
RPI_POWER_DOMAIN_I2C1
|
||||
RPI_POWER_DOMAIN_I2C2
|
||||
RPI_POWER_DOMAIN_VIDEO_SCALER
|
||||
RPI_POWER_DOMAIN_VPU1
|
||||
RPI_POWER_DOMAIN_HDMI
|
||||
RPI_POWER_DOMAIN_USB
|
||||
RPI_POWER_DOMAIN_VEC
|
||||
RPI_POWER_DOMAIN_JPEG
|
||||
RPI_POWER_DOMAIN_H264
|
||||
RPI_POWER_DOMAIN_V3D
|
||||
RPI_POWER_DOMAIN_ISP
|
||||
RPI_POWER_DOMAIN_UNICAM0
|
||||
RPI_POWER_DOMAIN_UNICAM1
|
||||
RPI_POWER_DOMAIN_CCP2RX
|
||||
RPI_POWER_DOMAIN_CSI2
|
||||
RPI_POWER_DOMAIN_CPI
|
||||
RPI_POWER_DOMAIN_DSI0
|
||||
RPI_POWER_DOMAIN_DSI1
|
||||
RPI_POWER_DOMAIN_TRANSPOSER
|
||||
RPI_POWER_DOMAIN_CCP2TX
|
||||
RPI_POWER_DOMAIN_CDP
|
||||
RPI_POWER_DOMAIN_ARM
|
||||
|
||||
Example:
|
||||
|
||||
power: power {
|
||||
compatible = "raspberrypi,bcm2835-power";
|
||||
firmware = <&firmware>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
Example for using power domain:
|
||||
|
||||
&usb {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_USB>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user