dt-bindings: mmc: sdhci-am654: Add documentation for input tap delay
Add documentation for input tap delay bindings. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -114,6 +114,46 @@ properties:
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minimum: 0
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maximum: 0xf
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# PHY input tap delays:
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# Used to delay the data valid window and align it to the sampling clock for
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# modes that don't support tuning
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ti,itap-del-sel-legacy:
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description: Input tap delay for SD/MMC legacy timing
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-mmc-hs:
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description: Input tap delay for MMC high speed timing
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-sd-hs:
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description: Input tap delay for SD high speed timing
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-sdr12:
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description: Input tap delay for SD UHS SDR12 timing
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-sdr25:
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description: Input tap delay for SD UHS SDR25 timing
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-ddr52:
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description: Input tap delay for MMC DDR52 timing
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 0x1f
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ti,trm-icp:
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description: DLL trim select
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$ref: "/schemas/types.yaml#/definitions/uint32"
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@ -170,6 +210,9 @@ examples:
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ti,otap-del-sel-ddr52 = <0x5>;
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ti,otap-del-sel-hs200 = <0x5>;
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ti,otap-del-sel-hs400 = <0x0>;
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ti,itap-del-sel-legacy = <0x10>;
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ti,itap-del-sel-mmc-hs = <0xa>;
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ti,itap-del-sel-ddr52 = <0x3>;
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ti,trm-icp = <0x8>;
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};
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};
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