drm/i915: Use the watermark latency values from dev_priv for ILK/SNB/IVB too
Adjust the current ILK/SNB/IVB watermark codepaths to use the pre-populated latency values from dev_priv instead of reading them out from the registers every time. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3196,9 +3196,6 @@
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#define MLTR_WM2_SHIFT 8
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/* the unit of memory self-refresh latency time is 0.5us */
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#define ILK_SRLT_MASK 0x3f
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#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
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#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
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#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
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/* define the fifo size on Ironlake */
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#define ILK_DISPLAY_FIFO 128
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@ -3245,12 +3242,6 @@
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#define SSKPD_WM2_SHIFT 16
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#define SSKPD_WM3_SHIFT 24
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#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
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#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
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#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
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#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
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#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
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/*
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* The two pipe frame counter registers are not synchronized, so
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* reading a stable value is somewhat tricky. The following code
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@ -1680,9 +1680,6 @@ static void i830_update_wm(struct drm_device *dev)
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I915_WRITE(FW_BLC, fwater_lo);
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}
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#define ILK_LP0_PLANE_LATENCY 700
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#define ILK_LP0_CURSOR_LATENCY 1300
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/*
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* Check the wm result.
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*
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@ -1797,9 +1794,9 @@ static void ironlake_update_wm(struct drm_device *dev)
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enabled = 0;
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if (g4x_compute_wm0(dev, PIPE_A,
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&ironlake_display_wm_info,
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ILK_LP0_PLANE_LATENCY,
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dev_priv->wm.pri_latency[0] * 100,
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&ironlake_cursor_wm_info,
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ILK_LP0_CURSOR_LATENCY,
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dev_priv->wm.cur_latency[0] * 100,
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&plane_wm, &cursor_wm)) {
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I915_WRITE(WM0_PIPEA_ILK,
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(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
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@ -1811,9 +1808,9 @@ static void ironlake_update_wm(struct drm_device *dev)
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if (g4x_compute_wm0(dev, PIPE_B,
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&ironlake_display_wm_info,
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ILK_LP0_PLANE_LATENCY,
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dev_priv->wm.pri_latency[0] * 100,
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&ironlake_cursor_wm_info,
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ILK_LP0_CURSOR_LATENCY,
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dev_priv->wm.cur_latency[0] * 100,
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&plane_wm, &cursor_wm)) {
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I915_WRITE(WM0_PIPEB_ILK,
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(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
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@ -1837,7 +1834,7 @@ static void ironlake_update_wm(struct drm_device *dev)
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/* WM1 */
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if (!ironlake_compute_srwm(dev, 1, enabled,
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ILK_READ_WM1_LATENCY() * 500,
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dev_priv->wm.pri_latency[1] * 500,
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&ironlake_display_srwm_info,
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&ironlake_cursor_srwm_info,
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&fbc_wm, &plane_wm, &cursor_wm))
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@ -1845,14 +1842,14 @@ static void ironlake_update_wm(struct drm_device *dev)
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I915_WRITE(WM1_LP_ILK,
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WM1_LP_SR_EN |
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(ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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/* WM2 */
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if (!ironlake_compute_srwm(dev, 2, enabled,
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ILK_READ_WM2_LATENCY() * 500,
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dev_priv->wm.pri_latency[2] * 500,
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&ironlake_display_srwm_info,
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&ironlake_cursor_srwm_info,
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&fbc_wm, &plane_wm, &cursor_wm))
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@ -1860,7 +1857,7 @@ static void ironlake_update_wm(struct drm_device *dev)
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I915_WRITE(WM2_LP_ILK,
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WM2_LP_EN |
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(ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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@ -1874,7 +1871,7 @@ static void ironlake_update_wm(struct drm_device *dev)
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static void sandybridge_update_wm(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
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int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
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u32 val;
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int fbc_wm, plane_wm, cursor_wm;
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unsigned int enabled;
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@ -1929,7 +1926,7 @@ static void sandybridge_update_wm(struct drm_device *dev)
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/* WM1 */
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if (!ironlake_compute_srwm(dev, 1, enabled,
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SNB_READ_WM1_LATENCY() * 500,
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dev_priv->wm.pri_latency[1] * 500,
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&sandybridge_display_srwm_info,
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&sandybridge_cursor_srwm_info,
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&fbc_wm, &plane_wm, &cursor_wm))
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@ -1937,14 +1934,14 @@ static void sandybridge_update_wm(struct drm_device *dev)
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I915_WRITE(WM1_LP_ILK,
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WM1_LP_SR_EN |
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(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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/* WM2 */
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if (!ironlake_compute_srwm(dev, 2, enabled,
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SNB_READ_WM2_LATENCY() * 500,
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dev_priv->wm.pri_latency[2] * 500,
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&sandybridge_display_srwm_info,
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&sandybridge_cursor_srwm_info,
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&fbc_wm, &plane_wm, &cursor_wm))
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@ -1952,14 +1949,14 @@ static void sandybridge_update_wm(struct drm_device *dev)
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I915_WRITE(WM2_LP_ILK,
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WM2_LP_EN |
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(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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/* WM3 */
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if (!ironlake_compute_srwm(dev, 3, enabled,
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SNB_READ_WM3_LATENCY() * 500,
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dev_priv->wm.pri_latency[3] * 500,
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&sandybridge_display_srwm_info,
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&sandybridge_cursor_srwm_info,
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&fbc_wm, &plane_wm, &cursor_wm))
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@ -1967,7 +1964,7 @@ static void sandybridge_update_wm(struct drm_device *dev)
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I915_WRITE(WM3_LP_ILK,
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WM3_LP_EN |
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(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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@ -1976,7 +1973,7 @@ static void sandybridge_update_wm(struct drm_device *dev)
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static void ivybridge_update_wm(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
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int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
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u32 val;
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int fbc_wm, plane_wm, cursor_wm;
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int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
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@ -2046,7 +2043,7 @@ static void ivybridge_update_wm(struct drm_device *dev)
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/* WM1 */
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if (!ironlake_compute_srwm(dev, 1, enabled,
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SNB_READ_WM1_LATENCY() * 500,
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dev_priv->wm.pri_latency[1] * 500,
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&sandybridge_display_srwm_info,
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&sandybridge_cursor_srwm_info,
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&fbc_wm, &plane_wm, &cursor_wm))
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@ -2054,14 +2051,14 @@ static void ivybridge_update_wm(struct drm_device *dev)
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I915_WRITE(WM1_LP_ILK,
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WM1_LP_SR_EN |
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(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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/* WM2 */
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if (!ironlake_compute_srwm(dev, 2, enabled,
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SNB_READ_WM2_LATENCY() * 500,
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dev_priv->wm.pri_latency[2] * 500,
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&sandybridge_display_srwm_info,
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&sandybridge_cursor_srwm_info,
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&fbc_wm, &plane_wm, &cursor_wm))
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@ -2069,19 +2066,19 @@ static void ivybridge_update_wm(struct drm_device *dev)
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I915_WRITE(WM2_LP_ILK,
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WM2_LP_EN |
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(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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/* WM3, note we have to correct the cursor latency */
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if (!ironlake_compute_srwm(dev, 3, enabled,
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SNB_READ_WM3_LATENCY() * 500,
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dev_priv->wm.pri_latency[3] * 500,
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&sandybridge_display_srwm_info,
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&sandybridge_cursor_srwm_info,
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&fbc_wm, &plane_wm, &ignore_cursor_wm) ||
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!ironlake_compute_srwm(dev, 3, enabled,
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2 * SNB_READ_WM3_LATENCY() * 500,
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dev_priv->wm.cur_latency[3] * 500,
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&sandybridge_display_srwm_info,
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&sandybridge_cursor_srwm_info,
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&ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
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@ -2089,7 +2086,7 @@ static void ivybridge_update_wm(struct drm_device *dev)
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I915_WRITE(WM3_LP_ILK,
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WM3_LP_EN |
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(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
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(dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
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(fbc_wm << WM1_LP_FBC_SHIFT) |
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(plane_wm << WM1_LP_SR_SHIFT) |
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cursor_wm);
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@ -2833,7 +2830,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
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bool enable, bool scaled)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
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int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
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u32 val;
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int sprite_wm, reg;
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int ret;
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@ -2873,7 +2870,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
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ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
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pixel_size,
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&sandybridge_display_srwm_info,
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SNB_READ_WM1_LATENCY() * 500,
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dev_priv->wm.spr_latency[1] * 500,
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&sprite_wm);
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if (!ret) {
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DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
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@ -2889,7 +2886,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
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ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
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pixel_size,
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&sandybridge_display_srwm_info,
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SNB_READ_WM2_LATENCY() * 500,
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dev_priv->wm.spr_latency[2] * 500,
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&sprite_wm);
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if (!ret) {
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DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
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@ -2901,7 +2898,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
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ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
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pixel_size,
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&sandybridge_display_srwm_info,
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SNB_READ_WM3_LATENCY() * 500,
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dev_priv->wm.spr_latency[3] * 500,
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&sprite_wm);
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if (!ret) {
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DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
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