Merge branch 'pm' into devel-stable
This commit is contained in:
commit
b0a37dca72
@ -81,6 +81,10 @@ extern void cpu_dcache_clean_area(void *, int);
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extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
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extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
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extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
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/* These three are private to arch/arm/kernel/suspend.c */
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extern void cpu_do_suspend(void *);
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extern void cpu_do_resume(void *);
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#else
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#define cpu_proc_init processor._proc_init
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#define cpu_proc_fin processor._proc_fin
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@ -89,6 +93,10 @@ extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
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#define cpu_dcache_clean_area processor.dcache_clean_area
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#define cpu_set_pte_ext processor.set_pte_ext
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#define cpu_do_switch_mm processor.switch_mm
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/* These three are private to arch/arm/kernel/suspend.c */
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#define cpu_do_suspend processor.do_suspend
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#define cpu_do_resume processor.do_resume
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#endif
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extern void cpu_resume(void);
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@ -1,22 +1,7 @@
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#ifndef __ASM_ARM_SUSPEND_H
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#define __ASM_ARM_SUSPEND_H
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#include <asm/memory.h>
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#include <asm/tlbflush.h>
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extern void cpu_resume(void);
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/*
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* Hide the first two arguments to __cpu_suspend - these are an implementation
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* detail which platform code shouldn't have to know about.
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*/
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static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
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{
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extern int __cpu_suspend(int, long, unsigned long,
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int (*)(unsigned long));
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int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
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flush_tlb_all();
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return ret;
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}
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extern int cpu_suspend(unsigned long, int (*)(unsigned long));
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#endif
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@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o
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obj-$(CONFIG_ARTHUR) += arthur.o
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obj-$(CONFIG_ISA_DMA) += dma-isa.o
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obj-$(CONFIG_PCI) += bios32.o isa.o
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obj-$(CONFIG_PM_SLEEP) += sleep.o
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obj-$(CONFIG_PM_SLEEP) += sleep.o suspend.o
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obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o
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obj-$(CONFIG_SMP) += smp.o smp_tlb.o
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obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
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@ -8,92 +8,61 @@
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.text
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/*
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* Save CPU state for a suspend
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* r1 = v:p offset
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* r2 = suspend function arg0
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* r3 = suspend function
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* Save CPU state for a suspend. This saves the CPU general purpose
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* registers, and allocates space on the kernel stack to save the CPU
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* specific registers and some other data for resume.
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* r0 = suspend function arg0
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* r1 = suspend function
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*/
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ENTRY(__cpu_suspend)
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stmfd sp!, {r4 - r11, lr}
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#ifdef MULTI_CPU
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ldr r10, =processor
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ldr r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
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ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function
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ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
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#else
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ldr r5, =cpu_suspend_size
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ldr ip, =cpu_do_resume
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ldr r4, =cpu_suspend_size
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#endif
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mov r6, sp @ current virtual SP
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sub sp, sp, r5 @ allocate CPU state on stack
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mov r0, sp @ save pointer to CPU save block
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add ip, ip, r1 @ convert resume fn to phys
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stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn
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ldr r5, =sleep_save_sp
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add r6, sp, r1 @ convert SP to phys
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stmfd sp!, {r2, r3} @ save suspend func arg and pointer
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mov r5, sp @ current virtual SP
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add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn
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sub sp, sp, r4 @ allocate CPU state on stack
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stmfd sp!, {r0, r1} @ save suspend func arg and pointer
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add r0, sp, #8 @ save pointer to save block
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mov r1, r4 @ size of save block
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mov r2, r5 @ virtual SP
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ldr r3, =sleep_save_sp
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
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ALT_UP(mov lr, #0)
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and lr, lr, #15
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str r6, [r5, lr, lsl #2] @ save phys SP
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#else
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str r6, [r5] @ save phys SP
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#endif
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#ifdef MULTI_CPU
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mov lr, pc
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ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
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#else
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bl cpu_do_suspend
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#endif
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@ flush data cache
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#ifdef MULTI_CACHE
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ldr r10, =cpu_cache
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mov lr, pc
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ldr pc, [r10, #CACHE_FLUSH_KERN_ALL]
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#else
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bl __cpuc_flush_kern_all
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add r3, r3, lr, lsl #2
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#endif
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bl __cpu_suspend_save
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adr lr, BSYM(cpu_suspend_abort)
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ldmfd sp!, {r0, pc} @ call suspend fn
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ENDPROC(__cpu_suspend)
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.ltorg
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cpu_suspend_abort:
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ldmia sp!, {r1 - r3} @ pop v:p, virt SP, phys resume fn
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ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
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teq r0, #0
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moveq r0, #1 @ force non-zero value
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mov sp, r2
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_suspend_abort)
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/*
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* r0 = control register value
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* r1 = v:p offset (preserved by cpu_do_resume)
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* r2 = phys page table base
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* r3 = L1 section flags
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*/
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ENTRY(cpu_resume_mmu)
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adr r4, cpu_resume_turn_mmu_on
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mov r4, r4, lsr #20
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orr r3, r3, r4, lsl #20
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ldr r5, [r2, r4, lsl #2] @ save old mapping
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str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code
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sub r2, r2, r1
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ldr r3, =cpu_resume_after_mmu
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bic r1, r0, #CR_C @ ensure D-cache is disabled
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b cpu_resume_turn_mmu_on
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ENDPROC(cpu_resume_mmu)
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.ltorg
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.align 5
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cpu_resume_turn_mmu_on:
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mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r1, c0, c0, 0 @ read id reg
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mov r1, r1
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mov r1, r1
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ENTRY(cpu_resume_mmu)
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ldr r3, =cpu_resume_after_mmu
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mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r0, c0, c0, 0 @ read id reg
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mov r0, r0
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mov r0, r0
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mov pc, r3 @ jump to virtual address
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ENDPROC(cpu_resume_turn_mmu_on)
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ENDPROC(cpu_resume_mmu)
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cpu_resume_after_mmu:
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str r5, [r2, r4, lsl #2] @ restore old mapping
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mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache
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bl cpu_init @ restore the und/abt/irq banked regs
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mov r0, #0 @ return zero on success
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ldmfd sp!, {r4 - r11, pc}
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@ -119,7 +88,7 @@ ENTRY(cpu_resume)
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ldr r0, sleep_save_sp @ stack phys addr
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#endif
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
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@ load v:p, stack, resume fn
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@ load phys pgd, stack, resume fn
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ARM( ldmia r0!, {r1, sp, pc} )
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THUMB( ldmia r0!, {r1, r2, r3} )
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THUMB( mov sp, r2 )
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72
arch/arm/kernel/suspend.c
Normal file
72
arch/arm/kernel/suspend.c
Normal file
@ -0,0 +1,72 @@
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#include <linux/init.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/memory.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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static pgd_t *suspend_pgd;
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extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
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extern void cpu_resume_mmu(void);
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/*
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* This is called by __cpu_suspend() to save the state, and do whatever
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* flushing is required to ensure that when the CPU goes to sleep we have
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* the necessary data available when the caches are not searched.
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*/
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void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
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{
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*save_ptr = virt_to_phys(ptr);
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/* This must correspond to the LDM in cpu_resume() assembly */
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*ptr++ = virt_to_phys(suspend_pgd);
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*ptr++ = sp;
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*ptr++ = virt_to_phys(cpu_do_resume);
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cpu_do_suspend(ptr);
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flush_cache_all();
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outer_clean_range(*save_ptr, *save_ptr + ptrsz);
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outer_clean_range(virt_to_phys(save_ptr),
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virt_to_phys(save_ptr) + sizeof(*save_ptr));
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}
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/*
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* Hide the first two arguments to __cpu_suspend - these are an implementation
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* detail which platform code shouldn't have to know about.
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*/
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int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
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{
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struct mm_struct *mm = current->active_mm;
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int ret;
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if (!suspend_pgd)
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return -EINVAL;
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/*
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* Provide a temporary page table with an identity mapping for
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* the MMU-enable code, required for resuming. On successful
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* resume (indicated by a zero return code), we need to switch
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* back to the correct page tables.
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*/
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ret = __cpu_suspend(arg, fn);
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if (ret == 0) {
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cpu_switch_mm(mm->pgd, mm);
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local_flush_tlb_all();
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}
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return ret;
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}
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static int __init cpu_suspend_init(void)
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{
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suspend_pgd = pgd_alloc(&init_mm);
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if (suspend_pgd) {
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unsigned long addr = virt_to_phys(cpu_resume_mmu);
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identity_mapping_add(suspend_pgd, addr, addr + SECTION_SIZE);
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}
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return suspend_pgd ? 0 : -ENOMEM;
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}
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core_initcall(cpu_suspend_init);
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@ -379,31 +379,26 @@ ENTRY(cpu_arm920_set_pte_ext)
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/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
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.globl cpu_arm920_suspend_size
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.equ cpu_arm920_suspend_size, 4 * 4
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.equ cpu_arm920_suspend_size, 4 * 3
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_arm920_do_suspend)
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stmfd sp!, {r4 - r7, lr}
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stmfd sp!, {r4 - r6, lr}
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mrc p15, 0, r4, c13, c0, 0 @ PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ TTB address
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mrc p15, 0, r7, c1, c0, 0 @ Control register
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stmia r0, {r4 - r7}
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ldmfd sp!, {r4 - r7, pc}
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mrc p15, 0, r6, c1, c0, 0 @ Control register
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stmia r0, {r4 - r6}
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(cpu_arm920_do_suspend)
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ENTRY(cpu_arm920_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
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ldmia r0, {r4 - r7}
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ldmia r0, {r4 - r6}
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mcr p15, 0, r4, c13, c0, 0 @ PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ TTB address
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mov r0, r7 @ control register
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mov r2, r6, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
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mcr p15, 0, r1, c2, c0, 0 @ TTB address
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mov r0, r6 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_arm920_do_resume)
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#endif
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@ -394,31 +394,26 @@ ENTRY(cpu_arm926_set_pte_ext)
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/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
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.globl cpu_arm926_suspend_size
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.equ cpu_arm926_suspend_size, 4 * 4
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.equ cpu_arm926_suspend_size, 4 * 3
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_arm926_do_suspend)
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stmfd sp!, {r4 - r7, lr}
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stmfd sp!, {r4 - r6, lr}
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mrc p15, 0, r4, c13, c0, 0 @ PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ TTB address
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mrc p15, 0, r7, c1, c0, 0 @ Control register
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stmia r0, {r4 - r7}
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ldmfd sp!, {r4 - r7, pc}
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mrc p15, 0, r6, c1, c0, 0 @ Control register
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stmia r0, {r4 - r6}
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(cpu_arm926_do_suspend)
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ENTRY(cpu_arm926_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
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ldmia r0, {r4 - r7}
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ldmia r0, {r4 - r6}
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mcr p15, 0, r4, c13, c0, 0 @ PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ TTB address
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mov r0, r7 @ control register
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mov r2, r6, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
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mcr p15, 0, r1, c2, c0, 0 @ TTB address
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mov r0, r6 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_arm926_do_resume)
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#endif
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|
@ -168,20 +168,19 @@ ENTRY(cpu_sa1100_set_pte_ext)
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mov pc, lr
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.globl cpu_sa1100_suspend_size
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.equ cpu_sa1100_suspend_size, 4*4
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.equ cpu_sa1100_suspend_size, 4 * 3
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_sa1100_do_suspend)
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stmfd sp!, {r4 - r7, lr}
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stmfd sp!, {r4 - r6, lr}
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mrc p15, 0, r4, c3, c0, 0 @ domain ID
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mrc p15, 0, r5, c2, c0, 0 @ translation table base addr
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mrc p15, 0, r6, c13, c0, 0 @ PID
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mrc p15, 0, r7, c1, c0, 0 @ control reg
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stmia r0, {r4 - r7} @ store cp regs
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ldmfd sp!, {r4 - r7, pc}
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mrc p15, 0, r5, c13, c0, 0 @ PID
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mrc p15, 0, r6, c1, c0, 0 @ control reg
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stmia r0, {r4 - r6} @ store cp regs
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(cpu_sa1100_do_suspend)
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ENTRY(cpu_sa1100_do_resume)
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ldmia r0, {r4 - r7} @ load cp regs
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ldmia r0, {r4 - r6} @ load cp regs
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
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@ -189,13 +188,9 @@ ENTRY(cpu_sa1100_do_resume)
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mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
|
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|
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mcr p15, 0, r4, c3, c0, 0 @ domain ID
|
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mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
|
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mcr p15, 0, r6, c13, c0, 0 @ PID
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mov r0, r7 @ control register
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mov r2, r5, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
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mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
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mcr p15, 0, r5, c13, c0, 0 @ PID
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mov r0, r6 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_sa1100_do_resume)
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#endif
|
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|
@ -128,20 +128,18 @@ ENTRY(cpu_v6_set_pte_ext)
|
||||
|
||||
/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
|
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.globl cpu_v6_suspend_size
|
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.equ cpu_v6_suspend_size, 4 * 8
|
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.equ cpu_v6_suspend_size, 4 * 6
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
ENTRY(cpu_v6_do_suspend)
|
||||
stmfd sp!, {r4 - r11, lr}
|
||||
stmfd sp!, {r4 - r9, lr}
|
||||
mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
|
||||
mrc p15, 0, r5, c13, c0, 1 @ Context ID
|
||||
mrc p15, 0, r6, c3, c0, 0 @ Domain ID
|
||||
mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0
|
||||
mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1
|
||||
mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register
|
||||
mrc p15, 0, r10, c1, c0, 2 @ co-processor access control
|
||||
mrc p15, 0, r11, c1, c0, 0 @ control register
|
||||
stmia r0, {r4 - r11}
|
||||
ldmfd sp!, {r4- r11, pc}
|
||||
mrc p15, 0, r5, c3, c0, 0 @ Domain ID
|
||||
mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
|
||||
mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
|
||||
mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
|
||||
mrc p15, 0, r9, c1, c0, 0 @ control register
|
||||
stmia r0, {r4 - r9}
|
||||
ldmfd sp!, {r4- r9, pc}
|
||||
ENDPROC(cpu_v6_do_suspend)
|
||||
|
||||
ENTRY(cpu_v6_do_resume)
|
||||
@ -150,25 +148,21 @@ ENTRY(cpu_v6_do_resume)
|
||||
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
||||
mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
|
||||
ldmia r0, {r4 - r11}
|
||||
mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
|
||||
ldmia r0, {r4 - r9}
|
||||
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
|
||||
mcr p15, 0, r5, c13, c0, 1 @ Context ID
|
||||
mcr p15, 0, r6, c3, c0, 0 @ Domain ID
|
||||
mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0
|
||||
mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1
|
||||
mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register
|
||||
mcr p15, 0, r10, c1, c0, 2 @ co-processor access control
|
||||
mcr p15, 0, r5, c3, c0, 0 @ Domain ID
|
||||
ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
|
||||
ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
|
||||
mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
|
||||
mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
|
||||
mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
|
||||
mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
|
||||
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
|
||||
mcr p15, 0, ip, c7, c5, 4 @ ISB
|
||||
mov r0, r11 @ control register
|
||||
mov r2, r7, lsr #14 @ get TTB0 base
|
||||
mov r2, r2, lsl #14
|
||||
ldr r3, cpu_resume_l1_flags
|
||||
mov r0, r9 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_v6_do_resume)
|
||||
cpu_resume_l1_flags:
|
||||
ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
|
||||
ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
|
||||
#endif
|
||||
|
||||
string cpu_v6_name, "ARMv6-compatible processor"
|
||||
|
@ -217,56 +217,50 @@ ENDPROC(cpu_v7_set_pte_ext)
|
||||
|
||||
/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
|
||||
.globl cpu_v7_suspend_size
|
||||
.equ cpu_v7_suspend_size, 4 * 9
|
||||
.equ cpu_v7_suspend_size, 4 * 7
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
ENTRY(cpu_v7_do_suspend)
|
||||
stmfd sp!, {r4 - r11, lr}
|
||||
stmfd sp!, {r4 - r10, lr}
|
||||
mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
|
||||
mrc p15, 0, r5, c13, c0, 1 @ Context ID
|
||||
mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
|
||||
stmia r0!, {r4 - r6}
|
||||
mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
|
||||
stmia r0!, {r4 - r5}
|
||||
mrc p15, 0, r6, c3, c0, 0 @ Domain ID
|
||||
mrc p15, 0, r7, c2, c0, 0 @ TTB 0
|
||||
mrc p15, 0, r8, c2, c0, 1 @ TTB 1
|
||||
mrc p15, 0, r9, c1, c0, 0 @ Control register
|
||||
mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
|
||||
mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
|
||||
stmia r0, {r6 - r11}
|
||||
ldmfd sp!, {r4 - r11, pc}
|
||||
mrc p15, 0, r7, c2, c0, 1 @ TTB 1
|
||||
mrc p15, 0, r8, c1, c0, 0 @ Control register
|
||||
mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
|
||||
mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
|
||||
stmia r0, {r6 - r10}
|
||||
ldmfd sp!, {r4 - r10, pc}
|
||||
ENDPROC(cpu_v7_do_suspend)
|
||||
|
||||
ENTRY(cpu_v7_do_resume)
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
|
||||
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
||||
ldmia r0!, {r4 - r6}
|
||||
mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
|
||||
ldmia r0!, {r4 - r5}
|
||||
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
|
||||
mcr p15, 0, r5, c13, c0, 1 @ Context ID
|
||||
mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
|
||||
ldmia r0, {r6 - r11}
|
||||
mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
|
||||
ldmia r0, {r6 - r10}
|
||||
mcr p15, 0, r6, c3, c0, 0 @ Domain ID
|
||||
mcr p15, 0, r7, c2, c0, 0 @ TTB 0
|
||||
mcr p15, 0, r8, c2, c0, 1 @ TTB 1
|
||||
ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
|
||||
ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
|
||||
mcr p15, 0, r1, c2, c0, 0 @ TTB 0
|
||||
mcr p15, 0, r7, c2, c0, 1 @ TTB 1
|
||||
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
|
||||
mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
|
||||
teq r4, r10 @ Is it already set?
|
||||
mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
|
||||
mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
|
||||
teq r4, r9 @ Is it already set?
|
||||
mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
|
||||
mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
|
||||
ldr r4, =PRRR @ PRRR
|
||||
ldr r5, =NMRR @ NMRR
|
||||
mcr p15, 0, r4, c10, c2, 0 @ write PRRR
|
||||
mcr p15, 0, r5, c10, c2, 1 @ write NMRR
|
||||
isb
|
||||
dsb
|
||||
mov r0, r9 @ control register
|
||||
mov r2, r7, lsr #14 @ get TTB0 base
|
||||
mov r2, r2, lsl #14
|
||||
ldr r3, cpu_resume_l1_flags
|
||||
mov r0, r8 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_v7_do_resume)
|
||||
cpu_resume_l1_flags:
|
||||
ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
|
||||
ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
|
||||
#endif
|
||||
|
||||
__CPUINIT
|
||||
|
@ -406,24 +406,23 @@ ENTRY(cpu_xsc3_set_pte_ext)
|
||||
.align
|
||||
|
||||
.globl cpu_xsc3_suspend_size
|
||||
.equ cpu_xsc3_suspend_size, 4 * 7
|
||||
.equ cpu_xsc3_suspend_size, 4 * 6
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
ENTRY(cpu_xsc3_do_suspend)
|
||||
stmfd sp!, {r4 - r10, lr}
|
||||
stmfd sp!, {r4 - r9, lr}
|
||||
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
|
||||
mrc p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mrc p15, 0, r6, c13, c0, 0 @ PID
|
||||
mrc p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
|
||||
mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
|
||||
mrc p15, 0, r10, c1, c0, 0 @ control reg
|
||||
mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
||||
mrc p15, 0, r9, c1, c0, 0 @ control reg
|
||||
bic r4, r4, #2 @ clear frequency change bit
|
||||
stmia r0, {r4 - r10} @ store cp regs
|
||||
ldmia sp!, {r4 - r10, pc}
|
||||
stmia r0, {r4 - r9} @ store cp regs
|
||||
ldmia sp!, {r4 - r9, pc}
|
||||
ENDPROC(cpu_xsc3_do_suspend)
|
||||
|
||||
ENTRY(cpu_xsc3_do_resume)
|
||||
ldmia r0, {r4 - r10} @ load cp regs
|
||||
ldmia r0, {r4 - r9} @ load cp regs
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
|
||||
@ -433,15 +432,10 @@ ENTRY(cpu_xsc3_do_resume)
|
||||
mcr p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mcr p15, 0, r6, c13, c0, 0 @ PID
|
||||
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg
|
||||
|
||||
@ temporarily map resume_turn_on_mmu into the page table,
|
||||
@ otherwise prefetch abort occurs after MMU is turned on
|
||||
mov r0, r10 @ control register
|
||||
mov r2, r8, lsr #14 @ get TTB0 base
|
||||
mov r2, r2, lsl #14
|
||||
ldr r3, =0x542e @ section flags
|
||||
orr r1, r1, #0x18 @ cache the page table in L2
|
||||
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
||||
mov r0, r9 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_xsc3_do_resume)
|
||||
#endif
|
||||
|
@ -520,24 +520,23 @@ ENTRY(cpu_xscale_set_pte_ext)
|
||||
.align
|
||||
|
||||
.globl cpu_xscale_suspend_size
|
||||
.equ cpu_xscale_suspend_size, 4 * 7
|
||||
.equ cpu_xscale_suspend_size, 4 * 6
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
ENTRY(cpu_xscale_do_suspend)
|
||||
stmfd sp!, {r4 - r10, lr}
|
||||
stmfd sp!, {r4 - r9, lr}
|
||||
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
|
||||
mrc p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mrc p15, 0, r6, c13, c0, 0 @ PID
|
||||
mrc p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
|
||||
mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg
|
||||
mrc p15, 0, r10, c1, c0, 0 @ control reg
|
||||
mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mrc p15, 0, r9, c1, c0, 0 @ control reg
|
||||
bic r4, r4, #2 @ clear frequency change bit
|
||||
stmia r0, {r4 - r10} @ store cp regs
|
||||
ldmfd sp!, {r4 - r10, pc}
|
||||
stmia r0, {r4 - r9} @ store cp regs
|
||||
ldmfd sp!, {r4 - r9, pc}
|
||||
ENDPROC(cpu_xscale_do_suspend)
|
||||
|
||||
ENTRY(cpu_xscale_do_resume)
|
||||
ldmia r0, {r4 - r10} @ load cp regs
|
||||
ldmia r0, {r4 - r9} @ load cp regs
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
|
||||
@ -545,13 +544,9 @@ ENTRY(cpu_xscale_do_resume)
|
||||
mcr p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mcr p15, 0, r6, c13, c0, 0 @ PID
|
||||
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg
|
||||
mov r0, r10 @ control register
|
||||
mov r2, r8, lsr #14 @ get TTB0 base
|
||||
mov r2, r2, lsl #14
|
||||
ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
|
||||
PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
|
||||
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mov r0, r9 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_xscale_do_resume)
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user