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drm/i915: All PCH refclks are 120MHz

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I can't find any reference clocks which run at 96MHz as seems to be
indicated from the comments in this code.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Keith Packard 2011-09-26 20:42:37 -07:00
parent 99eb6a01e5
commit afffb9dfb6
1 changed files with 4 additions and 10 deletions
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14
drivers/gpu/drm/i915/intel_display.c
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@ -5281,16 +5281,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
num_connectors++; num_connectors++;
} }
if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { /*
refclk = dev_priv->lvds_ssc_freq * 1000; * Every reference clock in a PCH system is 120MHz
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", */
refclk / 1000); refclk = 120000;
} else {
refclk = 96000;
if (!has_edp_encoder ||
intel_encoder_is_pch_edp(&has_edp_encoder->base))
refclk = 120000; /* 120Mhz refclk */
}
/* /*
* Returns a set of divisors for the desired target clock with the given * Returns a set of divisors for the desired target clock with the given