leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

clk: tegra: pll: Fix issues with rates for VCO PLLs

Browse Source 
Without this change clk_get_rate would return the final output
rather than the VCO output as it would factor in the pdiv when
it shouldn't. This will cause problems for all dividers in the
subtree of the VCO PLL.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Andrew Bresticker 2015-06-18 17:28:37 -04:00 committed by Thierry Reding
parent 6b301a059e
commit afff455cf4
1 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/clk/tegra/clk-pll.c
View File

@ -752,6 +752,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(pll->lock, flags);
_get_pll_mnp(pll, &old_cfg);
if (pll->params->flags & TEGRA_PLL_VCO_OUT)
cfg.p = old_cfg.p;
if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
old_cfg.sdm_data != cfg.sdm_data)
@ -812,11 +814,15 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
_get_pll_mnp(pll, &cfg);
pdiv = _hw_to_p_div(hw, cfg.p);
if (pdiv < 0) {
WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
__clk_get_name(hw->clk), cfg.p);
if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
pdiv = 1;
} else {
pdiv = _hw_to_p_div(hw, cfg.p);
if (pdiv < 0) {
WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
clk_hw_get_name(hw), cfg.p);
pdiv = 1;
}
}
if (pll->params->set_gain)
@ -1103,6 +1109,8 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(pll->lock, flags);
_get_pll_mnp(pll, &old_cfg);
if (pll->params->flags & TEGRA_PLL_VCO_OUT)
cfg.p = old_cfg.p;
if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
ret = _program_pll(hw, &cfg, rate);