forked from Minki/linux
Merge branch 'marco-timer-cleanup-rebase' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into next/soc
From Barry Song, this adds support for a new SoC from CSR; marco. It's SMP, uses GIC instead of VIC and in general needs a bit of rework of the platform code for setup, which this branch contains. * 'marco-timer-cleanup-rebase' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel: ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for Marco ARM: PRIMA2: rtciobg: it is also compatible with marco ARM: PRIMA2: rstc: enable the support for Marco ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco ARM: PRIMA2: initialize l2x0 according to mach from DT ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig ARM: PRIMA2: add CSR SiRFmarco device tree .dts Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
af70fdc947
@ -1,3 +1,9 @@
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prima2 "cb" evaluation board
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||||
CSR SiRFprimaII and SiRFmarco device tree bindings.
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||||
========================================
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Required root node properties:
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- compatible = "sirf,prima2-cb", "sirf,prima2";
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- compatible:
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- "sirf,prima2-cb" : prima2 "cb" evaluation board
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- "sirf,marco-cb" : marco "cb" evaluation board
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- "sirf,prima2" : prima2 device based board
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- "sirf,marco" : marco device based board
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@ -393,6 +393,7 @@ config ARCH_GEMINI
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config ARCH_SIRF
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bool "CSR SiRF"
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select ARCH_REQUIRE_GPIOLIB
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select AUTO_ZRELADDR
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_CHIP
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@ -386,6 +386,20 @@ choice
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Say Y here if you want kernel low-level debugging support
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on Tegra based platforms.
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config DEBUG_SIRFPRIMA2_UART1
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bool "Kernel low-level debugging messages via SiRFprimaII UART1"
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depends on ARCH_PRIMA2
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help
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Say Y here if you want the debug print routines to direct
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their output to the uart1 port on SiRFprimaII devices.
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config DEBUG_SIRFMARCO_UART1
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bool "Kernel low-level debugging messages via SiRFmarco UART1"
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depends on ARCH_MARCO
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help
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Say Y here if you want the debug print routines to direct
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their output to the uart1 port on SiRFmarco devices.
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config DEBUG_VEXPRESS_UART0_DETECT
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bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
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depends on ARCH_VEXPRESS && CPU_CP15_MMU
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@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
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kirkwood-ts219-6281.dtb \
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kirkwood-ts219-6282.dtb \
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kirkwood-openblocks_a6.dtb
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dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
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dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
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msm8960-cdp.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
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54
arch/arm/boot/dts/marco-evb.dts
Normal file
54
arch/arm/boot/dts/marco-evb.dts
Normal file
@ -0,0 +1,54 @@
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/*
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* DTS file for CSR SiRFmarco Evaluation Board
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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/dts-v1/;
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/include/ "marco.dtsi"
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/ {
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model = "CSR SiRFmarco Evaluation Board";
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compatible = "sirf,marco-cb", "sirf,marco";
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memory {
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reg = <0x40000000 0x60000000>;
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};
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axi {
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peri-iobg {
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uart1: uart@cc060000 {
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status = "okay";
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||||
};
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||||
uart2: uart@cc070000 {
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status = "okay";
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||||
};
|
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i2c0: i2c@cc0e0000 {
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status = "okay";
|
||||
fpga-cpld@4d {
|
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compatible = "sirf,fpga-cpld";
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reg = <0x4d>;
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};
|
||||
};
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spi1: spi@cc170000 {
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status = "okay";
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pinctrl-names = "default";
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||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
spi@0 {
|
||||
compatible = "spidev";
|
||||
reg = <0>;
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||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
pci-iobg {
|
||||
sd0: sdhci@cd000000 {
|
||||
bus-width = <8>;
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||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
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756
arch/arm/boot/dts/marco.dtsi
Normal file
756
arch/arm/boot/dts/marco.dtsi
Normal file
@ -0,0 +1,756 @@
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/*
|
||||
* DTS file for CSR SiRFmarco SoC
|
||||
*
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||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
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||||
|
||||
/include/ "skeleton.dtsi"
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/ {
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||||
compatible = "sirf,marco";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
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||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
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reg = <1>;
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||||
};
|
||||
};
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||||
|
||||
axi {
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||||
compatible = "simple-bus";
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#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x40000000 0xa0000000>;
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||||
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||||
l2-cache-controller@c0030000 {
|
||||
compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
|
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reg = <0xc0030000 0x1000>;
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||||
interrupts = <0 59 0>;
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||||
arm,tag-latency = <1 1 1>;
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arm,data-latency = <1 1 1>;
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||||
arm,filter-ranges = <0x40000000 0x80000000>;
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||||
};
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||||
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gic: interrupt-controller@c0011000 {
|
||||
compatible = "arm,cortex-a9-gic";
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||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xc0011000 0x1000>,
|
||||
<0xc0010100 0x0100>;
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||||
};
|
||||
|
||||
rstc-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc2000000 0xc2000000 0x1000000>;
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||||
|
||||
reset-controller@c2000000 {
|
||||
compatible = "sirf,marco-rstc";
|
||||
reg = <0xc2000000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
sys-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc3000000 0xc3000000 0x1000000>;
|
||||
|
||||
clock-controller@c3000000 {
|
||||
compatible = "sirf,marco-clkc";
|
||||
reg = <0xc3000000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
};
|
||||
|
||||
rsc-controller@c3010000 {
|
||||
compatible = "sirf,marco-rsc";
|
||||
reg = <0xc3010000 0x1000>;
|
||||
};
|
||||
};
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||||
|
||||
mem-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc4000000 0xc4000000 0x1000000>;
|
||||
|
||||
memory-controller@c4000000 {
|
||||
compatible = "sirf,marco-memc";
|
||||
reg = <0xc4000000 0x10000>;
|
||||
interrupts = <0 27 0>;
|
||||
};
|
||||
};
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||||
|
||||
disp-iobg0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc5000000 0xc5000000 0x1000000>;
|
||||
|
||||
display0@c5000000 {
|
||||
compatible = "sirf,marco-lcd";
|
||||
reg = <0xc5000000 0x10000>;
|
||||
interrupts = <0 30 0>;
|
||||
};
|
||||
|
||||
vpp0@c5010000 {
|
||||
compatible = "sirf,marco-vpp";
|
||||
reg = <0xc5010000 0x10000>;
|
||||
interrupts = <0 31 0>;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg1 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc6000000 0xc6000000 0x1000000>;
|
||||
|
||||
display1@c6000000 {
|
||||
compatible = "sirf,marco-lcd";
|
||||
reg = <0xc6000000 0x10000>;
|
||||
interrupts = <0 62 0>;
|
||||
};
|
||||
|
||||
vpp1@c6010000 {
|
||||
compatible = "sirf,marco-vpp";
|
||||
reg = <0xc6010000 0x10000>;
|
||||
interrupts = <0 63 0>;
|
||||
};
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc8000000 0xc8000000 0x1000000>;
|
||||
|
||||
graphics@c8000000 {
|
||||
compatible = "powervr,sgx540";
|
||||
reg = <0xc8000000 0x1000000>;
|
||||
interrupts = <0 6 0>;
|
||||
};
|
||||
};
|
||||
|
||||
multimedia-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc9000000 0xc9000000 0x1000000>;
|
||||
|
||||
multimedia@a0000000 {
|
||||
compatible = "sirf,marco-video-codec";
|
||||
reg = <0xc9000000 0x1000000>;
|
||||
interrupts = <0 5 0>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xca000000 0xca000000 0x2000000>;
|
||||
|
||||
dspif@ca000000 {
|
||||
compatible = "sirf,marco-dspif";
|
||||
reg = <0xca000000 0x10000>;
|
||||
interrupts = <0 9 0>;
|
||||
};
|
||||
|
||||
gps@ca010000 {
|
||||
compatible = "sirf,marco-gps";
|
||||
reg = <0xca010000 0x10000>;
|
||||
interrupts = <0 7 0>;
|
||||
};
|
||||
|
||||
dsp@cb000000 {
|
||||
compatible = "sirf,marco-dsp";
|
||||
reg = <0xcb000000 0x1000000>;
|
||||
interrupts = <0 8 0>;
|
||||
};
|
||||
};
|
||||
|
||||
peri-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xcc000000 0xcc000000 0x2000000>;
|
||||
|
||||
timer@cc020000 {
|
||||
compatible = "sirf,marco-tick";
|
||||
reg = <0xcc020000 0x1000>;
|
||||
interrupts = <0 0 0>,
|
||||
<0 1 0>,
|
||||
<0 2 0>,
|
||||
<0 49 0>,
|
||||
<0 50 0>,
|
||||
<0 51 0>;
|
||||
};
|
||||
|
||||
nand@cc030000 {
|
||||
compatible = "sirf,marco-nand";
|
||||
reg = <0xcc030000 0x10000>;
|
||||
interrupts = <0 41 0>;
|
||||
};
|
||||
|
||||
audio@cc040000 {
|
||||
compatible = "sirf,marco-audio";
|
||||
reg = <0xcc040000 0x10000>;
|
||||
interrupts = <0 35 0>;
|
||||
};
|
||||
|
||||
uart0: uart@cc050000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc050000 0x1000>;
|
||||
interrupts = <0 17 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@cc060000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc060000 0x1000>;
|
||||
interrupts = <0 18 0>;
|
||||
fifosize = <32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@cc070000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc070000 0x1000>;
|
||||
interrupts = <0 19 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@cc190000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc190000 0x1000>;
|
||||
interrupts = <0 66 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: uart@cc1a0000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc1a0000 0x1000>;
|
||||
interrupts = <0 69 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp0: usp@cc080000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-usp";
|
||||
reg = <0xcc080000 0x10000>;
|
||||
interrupts = <0 20 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp1: usp@cc090000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-usp";
|
||||
reg = <0xcc090000 0x10000>;
|
||||
interrupts = <0 21 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp2: usp@cc0a0000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,marco-usp";
|
||||
reg = <0xcc0a0000 0x10000>;
|
||||
interrupts = <0 22 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac0: dma-controller@cc0b0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-dmac";
|
||||
reg = <0xcc0b0000 0x10000>;
|
||||
interrupts = <0 12 0>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@cc160000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-dmac";
|
||||
reg = <0xcc160000 0x10000>;
|
||||
interrupts = <0 13 0>;
|
||||
};
|
||||
|
||||
vip@cc0c0000 {
|
||||
compatible = "sirf,marco-vip";
|
||||
reg = <0xcc0c0000 0x10000>;
|
||||
};
|
||||
|
||||
spi0: spi@cc0d0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-spi";
|
||||
reg = <0xcc0d0000 0x10000>;
|
||||
interrupts = <0 15 0>;
|
||||
sirf,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio 0 0>;
|
||||
sirf,spi-dma-rx-channel = <25>;
|
||||
sirf,spi-dma-tx-channel = <20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@cc170000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-spi";
|
||||
reg = <0xcc170000 0x10000>;
|
||||
interrupts = <0 16 0>;
|
||||
sirf,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio 0 0>;
|
||||
sirf,spi-dma-rx-channel = <12>;
|
||||
sirf,spi-dma-tx-channel = <13>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@cc0e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-i2c";
|
||||
reg = <0xcc0e0000 0x10000>;
|
||||
interrupts = <0 24 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@cc0f0000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-i2c";
|
||||
reg = <0xcc0f0000 0x10000>;
|
||||
interrupts = <0 25 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsc@cc110000 {
|
||||
compatible = "sirf,marco-tsc";
|
||||
reg = <0xcc110000 0x10000>;
|
||||
interrupts = <0 33 0>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@cc120000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,marco-pinctrl";
|
||||
reg = <0xcc120000 0x10000>;
|
||||
interrupts = <0 43 0>,
|
||||
<0 44 0>,
|
||||
<0 45 0>,
|
||||
<0 46 0>,
|
||||
<0 47 0>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
||||
lcd_16pins_a: lcd0_0 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_16bitsgrp";
|
||||
sirf,function = "lcd_16bits";
|
||||
};
|
||||
};
|
||||
lcd_18pins_a: lcd0_1 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_18bitsgrp";
|
||||
sirf,function = "lcd_18bits";
|
||||
};
|
||||
};
|
||||
lcd_24pins_a: lcd0_2 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_24bitsgrp";
|
||||
sirf,function = "lcd_24bits";
|
||||
};
|
||||
};
|
||||
lcdrom_pins_a: lcdrom0_0 {
|
||||
lcd {
|
||||
sirf,pins = "lcdromgrp";
|
||||
sirf,function = "lcdrom";
|
||||
};
|
||||
};
|
||||
uart0_pins_a: uart0_0 {
|
||||
uart {
|
||||
sirf,pins = "uart0grp";
|
||||
sirf,function = "uart0";
|
||||
};
|
||||
};
|
||||
uart1_pins_a: uart1_0 {
|
||||
uart {
|
||||
sirf,pins = "uart1grp";
|
||||
sirf,function = "uart1";
|
||||
};
|
||||
};
|
||||
uart2_pins_a: uart2_0 {
|
||||
uart {
|
||||
sirf,pins = "uart2grp";
|
||||
sirf,function = "uart2";
|
||||
};
|
||||
};
|
||||
uart2_noflow_pins_a: uart2_1 {
|
||||
uart {
|
||||
sirf,pins = "uart2_nostreamctrlgrp";
|
||||
sirf,function = "uart2_nostreamctrl";
|
||||
};
|
||||
};
|
||||
spi0_pins_a: spi0_0 {
|
||||
spi {
|
||||
sirf,pins = "spi0grp";
|
||||
sirf,function = "spi0";
|
||||
};
|
||||
};
|
||||
spi1_pins_a: spi1_0 {
|
||||
spi {
|
||||
sirf,pins = "spi1grp";
|
||||
sirf,function = "spi1";
|
||||
};
|
||||
};
|
||||
i2c0_pins_a: i2c0_0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c0grp";
|
||||
sirf,function = "i2c0";
|
||||
};
|
||||
};
|
||||
i2c1_pins_a: i2c1_0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c1grp";
|
||||
sirf,function = "i2c1";
|
||||
};
|
||||
};
|
||||
pwm0_pins_a: pwm0_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm0grp";
|
||||
sirf,function = "pwm0";
|
||||
};
|
||||
};
|
||||
pwm1_pins_a: pwm1_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm1grp";
|
||||
sirf,function = "pwm1";
|
||||
};
|
||||
};
|
||||
pwm2_pins_a: pwm2_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm2grp";
|
||||
sirf,function = "pwm2";
|
||||
};
|
||||
};
|
||||
pwm3_pins_a: pwm3_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm3grp";
|
||||
sirf,function = "pwm3";
|
||||
};
|
||||
};
|
||||
gps_pins_a: gps_0 {
|
||||
gps {
|
||||
sirf,pins = "gpsgrp";
|
||||
sirf,function = "gps";
|
||||
};
|
||||
};
|
||||
vip_pins_a: vip_0 {
|
||||
vip {
|
||||
sirf,pins = "vipgrp";
|
||||
sirf,function = "vip";
|
||||
};
|
||||
};
|
||||
sdmmc0_pins_a: sdmmc0_0 {
|
||||
sdmmc0 {
|
||||
sirf,pins = "sdmmc0grp";
|
||||
sirf,function = "sdmmc0";
|
||||
};
|
||||
};
|
||||
sdmmc1_pins_a: sdmmc1_0 {
|
||||
sdmmc1 {
|
||||
sirf,pins = "sdmmc1grp";
|
||||
sirf,function = "sdmmc1";
|
||||
};
|
||||
};
|
||||
sdmmc2_pins_a: sdmmc2_0 {
|
||||
sdmmc2 {
|
||||
sirf,pins = "sdmmc2grp";
|
||||
sirf,function = "sdmmc2";
|
||||
};
|
||||
};
|
||||
sdmmc3_pins_a: sdmmc3_0 {
|
||||
sdmmc3 {
|
||||
sirf,pins = "sdmmc3grp";
|
||||
sirf,function = "sdmmc3";
|
||||
};
|
||||
};
|
||||
sdmmc4_pins_a: sdmmc4_0 {
|
||||
sdmmc4 {
|
||||
sirf,pins = "sdmmc4grp";
|
||||
sirf,function = "sdmmc4";
|
||||
};
|
||||
};
|
||||
sdmmc5_pins_a: sdmmc5_0 {
|
||||
sdmmc5 {
|
||||
sirf,pins = "sdmmc5grp";
|
||||
sirf,function = "sdmmc5";
|
||||
};
|
||||
};
|
||||
i2s_pins_a: i2s_0 {
|
||||
i2s {
|
||||
sirf,pins = "i2sgrp";
|
||||
sirf,function = "i2s";
|
||||
};
|
||||
};
|
||||
ac97_pins_a: ac97_0 {
|
||||
ac97 {
|
||||
sirf,pins = "ac97grp";
|
||||
sirf,function = "ac97";
|
||||
};
|
||||
};
|
||||
nand_pins_a: nand_0 {
|
||||
nand {
|
||||
sirf,pins = "nandgrp";
|
||||
sirf,function = "nand";
|
||||
};
|
||||
};
|
||||
usp0_pins_a: usp0_0 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0grp";
|
||||
sirf,function = "usp0";
|
||||
};
|
||||
};
|
||||
usp1_pins_a: usp1_0 {
|
||||
usp1 {
|
||||
sirf,pins = "usp1grp";
|
||||
sirf,function = "usp1";
|
||||
};
|
||||
};
|
||||
usp2_pins_a: usp2_0 {
|
||||
usp2 {
|
||||
sirf,pins = "usp2grp";
|
||||
sirf,function = "usp2";
|
||||
};
|
||||
};
|
||||
usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
|
||||
usb0_utmi_drvbus {
|
||||
sirf,pins = "usb0_utmi_drvbusgrp";
|
||||
sirf,function = "usb0_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
|
||||
usb1_utmi_drvbus {
|
||||
sirf,pins = "usb1_utmi_drvbusgrp";
|
||||
sirf,function = "usb1_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
warm_rst_pins_a: warm_rst_0 {
|
||||
warm_rst {
|
||||
sirf,pins = "warm_rstgrp";
|
||||
sirf,function = "warm_rst";
|
||||
};
|
||||
};
|
||||
pulse_count_pins_a: pulse_count_0 {
|
||||
pulse_count {
|
||||
sirf,pins = "pulse_countgrp";
|
||||
sirf,function = "pulse_count";
|
||||
};
|
||||
};
|
||||
cko0_rst_pins_a: cko0_rst_0 {
|
||||
cko0_rst {
|
||||
sirf,pins = "cko0_rstgrp";
|
||||
sirf,function = "cko0_rst";
|
||||
};
|
||||
};
|
||||
cko1_rst_pins_a: cko1_rst_0 {
|
||||
cko1_rst {
|
||||
sirf,pins = "cko1_rstgrp";
|
||||
sirf,function = "cko1_rst";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm@cc130000 {
|
||||
compatible = "sirf,marco-pwm";
|
||||
reg = <0xcc130000 0x10000>;
|
||||
};
|
||||
|
||||
efusesys@cc140000 {
|
||||
compatible = "sirf,marco-efuse";
|
||||
reg = <0xcc140000 0x10000>;
|
||||
};
|
||||
|
||||
pulsec@cc150000 {
|
||||
compatible = "sirf,marco-pulsec";
|
||||
reg = <0xcc150000 0x10000>;
|
||||
interrupts = <0 48 0>;
|
||||
};
|
||||
|
||||
pci-iobg {
|
||||
compatible = "sirf,marco-pciiobg", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xcd000000 0xcd000000 0x1000000>;
|
||||
|
||||
sd0: sdhci@cd000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd000000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd1: sdhci@cd100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd100000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd2: sdhci@cd200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd200000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd3: sdhci@cd300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd300000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd4: sdhci@cd400000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd400000 0x100000>;
|
||||
interrupts = <0 39 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd5: sdhci@cd500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd500000 0x100000>;
|
||||
interrupts = <0 39 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci-copy@cd900000 {
|
||||
compatible = "sirf,marco-pcicp";
|
||||
reg = <0xcd900000 0x100000>;
|
||||
interrupts = <0 40 0>;
|
||||
};
|
||||
|
||||
rom-interface@cda00000 {
|
||||
compatible = "sirf,marco-romif";
|
||||
reg = <0xcda00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc-iobg {
|
||||
compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xc1000000 0x10000>;
|
||||
|
||||
gpsrtc@1000 {
|
||||
compatible = "sirf,marco-gpsrtc";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <0 55 0>,
|
||||
<0 56 0>,
|
||||
<0 57 0>;
|
||||
};
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,marco-sysrtc";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <0 52 0>,
|
||||
<0 53 0>,
|
||||
<0 54 0>;
|
||||
};
|
||||
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,marco-pwrc";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <0 32 0>;
|
||||
};
|
||||
};
|
||||
|
||||
uus-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xce000000 0xce000000 0x1000000>;
|
||||
|
||||
usb0: usb@ce000000 {
|
||||
compatible = "chipidea,ci13611a-marco";
|
||||
reg = <0xce000000 0x10000>;
|
||||
interrupts = <0 10 0>;
|
||||
};
|
||||
|
||||
usb1: usb@ce010000 {
|
||||
compatible = "chipidea,ci13611a-marco";
|
||||
reg = <0xce010000 0x10000>;
|
||||
interrupts = <0 11 0>;
|
||||
};
|
||||
|
||||
security@ce020000 {
|
||||
compatible = "sirf,marco-security";
|
||||
reg = <0xce020000 0x10000>;
|
||||
interrupts = <0 42 0>;
|
||||
};
|
||||
};
|
||||
|
||||
can-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xd0000000 0xd0000000 0x1000000>;
|
||||
|
||||
can0: can@d0000000 {
|
||||
compatible = "sirf,marco-can";
|
||||
reg = <0xd0000000 0x10000>;
|
||||
};
|
||||
|
||||
can1: can@d0010000 {
|
||||
compatible = "sirf,marco-can";
|
||||
reg = <0xd0010000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
lvds-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xd1000000 0xd1000000 0x1000000>;
|
||||
|
||||
lvds@d1000000 {
|
||||
compatible = "sirf,marco-lvds";
|
||||
reg = <0xd1000000 0x10000>;
|
||||
interrupts = <0 64 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -11,6 +11,9 @@ CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_BSD_DISKLABEL=y
|
||||
CONFIG_SOLARIS_X86_PARTITION=y
|
||||
CONFIG_ARCH_SIRF=y
|
||||
# CONFIG_SWP_EMULATE is not set
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_KEXEC=y
|
||||
|
||||
@ -11,6 +11,16 @@ config ARCH_PRIMA2
|
||||
help
|
||||
Support for CSR SiRFSoC ARM Cortex A9 Platform
|
||||
|
||||
config ARCH_MARCO
|
||||
bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
|
||||
default y
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select HAVE_SMP
|
||||
select SMP_ON_UP
|
||||
help
|
||||
Support for CSR SiRFSoC ARM Cortex A9 Platform
|
||||
|
||||
endmenu
|
||||
|
||||
config SIRF_IRQ
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
obj-y := timer.o
|
||||
obj-y += rstc.o
|
||||
obj-y += common.o
|
||||
obj-y += rtciobrg.o
|
||||
@ -6,3 +5,7 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
|
||||
obj-$(CONFIG_CACHE_L2X0) += l2x0.o
|
||||
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
|
||||
obj-$(CONFIG_SIRF_IRQ) += irq.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
|
||||
obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
|
||||
|
||||
@ -8,9 +8,11 @@
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include "common.h"
|
||||
@ -30,6 +32,12 @@ void __init sirfsoc_init_late(void)
|
||||
sirfsoc_pm_init();
|
||||
}
|
||||
|
||||
static __init void sirfsoc_map_io(void)
|
||||
{
|
||||
sirfsoc_map_lluart();
|
||||
sirfsoc_map_scu();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_PRIMA2
|
||||
static const char *prima2_dt_match[] __initdata = {
|
||||
"sirf,prima2",
|
||||
@ -38,9 +46,12 @@ static const char *prima2_dt_match[] __initdata = {
|
||||
|
||||
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
|
||||
/* Maintainer: Barry Song <baohua.song@csr.com> */
|
||||
.map_io = sirfsoc_map_lluart,
|
||||
.map_io = sirfsoc_map_io,
|
||||
.init_irq = sirfsoc_of_irq_init,
|
||||
.init_time = sirfsoc_timer_init,
|
||||
.init_time = sirfsoc_prima2_timer_init,
|
||||
#ifdef CONFIG_MULTI_IRQ_HANDLER
|
||||
.handle_irq = sirfsoc_handle_irq,
|
||||
#endif
|
||||
.dma_zone_size = SZ_256M,
|
||||
.init_machine = sirfsoc_mach_init,
|
||||
.init_late = sirfsoc_init_late,
|
||||
@ -48,3 +59,33 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
|
||||
.restart = sirfsoc_restart,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_MARCO
|
||||
static const struct of_device_id marco_irq_match[] __initconst = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init marco_init_irq(void)
|
||||
{
|
||||
of_irq_init(marco_irq_match);
|
||||
}
|
||||
|
||||
static const char *marco_dt_match[] __initdata = {
|
||||
"sirf,marco",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
|
||||
/* Maintainer: Barry Song <baohua.song@csr.com> */
|
||||
.smp = smp_ops(sirfsoc_smp_ops),
|
||||
.map_io = sirfsoc_map_io,
|
||||
.init_irq = marco_init_irq,
|
||||
.init_time = sirfsoc_marco_timer_init,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = sirfsoc_mach_init,
|
||||
.init_late = sirfsoc_init_late,
|
||||
.dt_compat = marco_dt_match,
|
||||
.restart = sirfsoc_restart,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
||||
@ -11,12 +11,19 @@
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/exception.h>
|
||||
|
||||
extern void sirfsoc_timer_init(void);
|
||||
extern void sirfsoc_prima2_timer_init(void);
|
||||
extern void sirfsoc_marco_timer_init(void);
|
||||
|
||||
extern struct smp_operations sirfsoc_smp_ops;
|
||||
extern void sirfsoc_secondary_startup(void);
|
||||
extern void sirfsoc_cpu_die(unsigned int cpu);
|
||||
|
||||
extern void __init sirfsoc_of_irq_init(void);
|
||||
extern void __init sirfsoc_of_clk_init(void);
|
||||
extern void sirfsoc_restart(char, const char *);
|
||||
extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
|
||||
|
||||
#ifndef CONFIG_DEBUG_LL
|
||||
static inline void sirfsoc_map_lluart(void) {}
|
||||
@ -24,6 +31,12 @@ static inline void sirfsoc_map_lluart(void) {}
|
||||
extern void __init sirfsoc_map_lluart(void);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
static inline void sirfsoc_map_scu(void) {}
|
||||
#else
|
||||
extern void sirfsoc_map_scu(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
extern int sirfsoc_pm_init(void);
|
||||
#else
|
||||
|
||||
79
arch/arm/mach-prima2/headsmp.S
Normal file
79
arch/arm/mach-prima2/headsmp.S
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Entry of the second core for CSR Marco dual-core SMP SoCs
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
__INIT
|
||||
/*
|
||||
* Cold boot and hardware reset show different behaviour,
|
||||
* system will be always panic if we warm-reset the board
|
||||
* Here we invalidate L1 of CPU1 to make sure there isn't
|
||||
* uninitialized data written into memory later
|
||||
*/
|
||||
ENTRY(v7_invalidate_l1)
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
|
||||
mcr p15, 2, r0, c0, c0, 0
|
||||
mrc p15, 1, r0, c0, c0, 0
|
||||
|
||||
ldr r1, =0x7fff
|
||||
and r2, r1, r0, lsr #13
|
||||
|
||||
ldr r1, =0x3ff
|
||||
|
||||
and r3, r1, r0, lsr #3 @ NumWays - 1
|
||||
add r2, r2, #1 @ NumSets
|
||||
|
||||
and r0, r0, #0x7
|
||||
add r0, r0, #4 @ SetShift
|
||||
|
||||
clz r1, r3 @ WayShift
|
||||
add r4, r3, #1 @ NumWays
|
||||
1: sub r2, r2, #1 @ NumSets--
|
||||
mov r3, r4 @ Temp = NumWays
|
||||
2: subs r3, r3, #1 @ Temp--
|
||||
mov r5, r3, lsl r1
|
||||
mov r6, r2, lsl r0
|
||||
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
|
||||
mcr p15, 0, r5, c7, c6, 2
|
||||
bgt 2b
|
||||
cmp r2, #0
|
||||
bgt 1b
|
||||
dsb
|
||||
isb
|
||||
mov pc, lr
|
||||
ENDPROC(v7_invalidate_l1)
|
||||
|
||||
/*
|
||||
* SIRFSOC specific entry point for secondary CPUs. This provides
|
||||
* a "holding pen" into which all secondary cores are held until we're
|
||||
* ready for them to initialise.
|
||||
*/
|
||||
ENTRY(sirfsoc_secondary_startup)
|
||||
bl v7_invalidate_l1
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #15
|
||||
adr r4, 1f
|
||||
ldmia r4, {r5, r6}
|
||||
sub r4, r4, r5
|
||||
add r6, r6, r4
|
||||
pen: ldr r7, [r6]
|
||||
cmp r7, r0
|
||||
bne pen
|
||||
|
||||
/*
|
||||
* we've been released from the holding pen: secondary_stack
|
||||
* should now contain the SVC stack for this core
|
||||
*/
|
||||
b secondary_startup
|
||||
ENDPROC(sirfsoc_secondary_startup)
|
||||
|
||||
.align
|
||||
1: .long .
|
||||
.long pen_release
|
||||
41
arch/arm/mach-prima2/hotplug.c
Normal file
41
arch/arm/mach-prima2/hotplug.c
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* CPU hotplug support for CSR Marco dual-core SMP SoCs
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
static inline void platform_do_lowpower(unsigned int cpu)
|
||||
{
|
||||
flush_cache_all();
|
||||
|
||||
/* we put the platform to just WFI */
|
||||
for (;;) {
|
||||
__asm__ __volatile__("dsb\n\t" "wfi\n\t"
|
||||
: : : "memory");
|
||||
if (pen_release == cpu_logical_map(cpu)) {
|
||||
/*
|
||||
* OK, proper wakeup, we're done
|
||||
*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* platform-specific code to shutdown a CPU
|
||||
*
|
||||
* Called with IRQs disabled
|
||||
*/
|
||||
void sirfsoc_cpu_die(unsigned int cpu)
|
||||
{
|
||||
platform_do_lowpower(cpu);
|
||||
}
|
||||
@ -10,8 +10,8 @@
|
||||
#define __ASM_ARCH_IRQS_H
|
||||
|
||||
#define SIRFSOC_INTENAL_IRQ_START 0
|
||||
#define SIRFSOC_INTENAL_IRQ_END 59
|
||||
#define SIRFSOC_INTENAL_IRQ_END 127
|
||||
#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)
|
||||
#define NR_IRQS 220
|
||||
#define NR_IRQS 288
|
||||
|
||||
#endif
|
||||
|
||||
@ -10,7 +10,13 @@
|
||||
#define __MACH_PRIMA2_SIRFSOC_UART_H
|
||||
|
||||
/* UART-1: used as serial debug port */
|
||||
#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
|
||||
#define SIRFSOC_UART1_PA_BASE 0xb0060000
|
||||
#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
|
||||
#define SIRFSOC_UART1_PA_BASE 0xcc060000
|
||||
#else
|
||||
#define SIRFSOC_UART1_PA_BASE 0
|
||||
#endif
|
||||
#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
|
||||
#define SIRFSOC_UART1_SIZE SZ_4K
|
||||
|
||||
|
||||
@ -25,6 +25,9 @@ static __inline__ void putc(char c)
|
||||
* during kernel decompression, all mappings are flat:
|
||||
* virt_addr == phys_addr
|
||||
*/
|
||||
if (!SIRFSOC_UART1_PA_BASE)
|
||||
return;
|
||||
|
||||
while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
|
||||
& SIRFSOC_UART1_TXFIFO_FULL)
|
||||
barrier();
|
||||
|
||||
@ -9,17 +9,19 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/exception.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define SIRFSOC_INT_RISC_MASK0 0x0018
|
||||
#define SIRFSOC_INT_RISC_MASK1 0x001C
|
||||
#define SIRFSOC_INT_RISC_LEVEL0 0x0020
|
||||
#define SIRFSOC_INT_RISC_LEVEL1 0x0024
|
||||
#define SIRFSOC_INIT_IRQ_ID 0x0038
|
||||
|
||||
void __iomem *sirfsoc_intc_base;
|
||||
|
||||
@ -52,6 +54,16 @@ static __init void sirfsoc_irq_init(void)
|
||||
writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
|
||||
}
|
||||
|
||||
asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
u32 irqstat, irqnr;
|
||||
|
||||
irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
|
||||
irqnr = irqstat & 0xff;
|
||||
|
||||
handle_IRQ(irqnr, regs);
|
||||
}
|
||||
|
||||
static struct of_device_id intc_ids[] = {
|
||||
{ .compatible = "sirf,prima2-intc" },
|
||||
{},
|
||||
|
||||
@ -11,19 +11,38 @@
|
||||
#include <linux/of.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
static struct of_device_id prima2_l2x0_ids[] = {
|
||||
{ .compatible = "sirf,prima2-pl310-cache" },
|
||||
struct l2x0_aux
|
||||
{
|
||||
u32 val;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
static struct l2x0_aux prima2_l2x0_aux __initconst = {
|
||||
.val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT,
|
||||
.mask = 0,
|
||||
};
|
||||
|
||||
static struct l2x0_aux marco_l2x0_aux __initconst = {
|
||||
.val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
|
||||
(1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT),
|
||||
.mask = L2X0_AUX_CTRL_MASK,
|
||||
};
|
||||
|
||||
static struct of_device_id sirf_l2x0_ids[] __initconst = {
|
||||
{ .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, },
|
||||
{ .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init sirfsoc_l2x0_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const struct l2x0_aux *aux;
|
||||
|
||||
np = of_find_matching_node(NULL, prima2_l2x0_ids);
|
||||
np = of_find_matching_node(NULL, sirf_l2x0_ids);
|
||||
if (np) {
|
||||
pr_info("Initializing prima2 L2 cache\n");
|
||||
return l2x0_of_init(0x40000, 0);
|
||||
aux = of_match_node(sirf_l2x0_ids, np)->data;
|
||||
return l2x0_of_init(aux->val, aux->mask);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
163
arch/arm/mach-prima2/platsmp.c
Normal file
163
arch/arm/mach-prima2/platsmp.c
Normal file
@ -0,0 +1,163 @@
|
||||
/*
|
||||
* plat smp support for CSR Marco dual-core SMP SoCs
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static void __iomem *scu_base;
|
||||
static void __iomem *rsc_base;
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
static struct map_desc scu_io_desc __initdata = {
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
};
|
||||
|
||||
void __init sirfsoc_map_scu(void)
|
||||
{
|
||||
unsigned long base;
|
||||
|
||||
/* Get SCU base */
|
||||
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
|
||||
|
||||
scu_io_desc.virtual = SIRFSOC_VA(base);
|
||||
scu_io_desc.pfn = __phys_to_pfn(base);
|
||||
iotable_init(&scu_io_desc, 1);
|
||||
|
||||
scu_base = (void __iomem *)SIRFSOC_VA(base);
|
||||
}
|
||||
|
||||
static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
*/
|
||||
pen_release = -1;
|
||||
smp_wmb();
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
static struct of_device_id rsc_ids[] = {
|
||||
{ .compatible = "sirf,marco-rsc" },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_matching_node(NULL, rsc_ids);
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
rsc_base = of_iomap(np, 0);
|
||||
if (!rsc_base)
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* write the address of secondary startup into the sram register
|
||||
* at offset 0x2C, then write the magic number 0x3CAF5D62 to the
|
||||
* RSC register at offset 0x28, which is what boot rom code is
|
||||
* waiting for. This would wake up the secondary core from WFE
|
||||
*/
|
||||
#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
|
||||
__raw_writel(virt_to_phys(sirfsoc_secondary_startup),
|
||||
rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
|
||||
|
||||
#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
|
||||
__raw_writel(0x3CAF5D62,
|
||||
rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
|
||||
|
||||
/* make sure write buffer is drained */
|
||||
mb();
|
||||
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/*
|
||||
* The secondary processor is waiting to be released from
|
||||
* the holding pen - release it, then wait for it to flag
|
||||
* that it has been released by resetting pen_release.
|
||||
*
|
||||
* Note that "pen_release" is the hardware CPU ID, whereas
|
||||
* "cpu" is Linux's internal ID.
|
||||
*/
|
||||
pen_release = cpu_logical_map(cpu);
|
||||
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
|
||||
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
|
||||
|
||||
/*
|
||||
* Send the secondary CPU SEV, thereby causing the boot monitor to read
|
||||
* the JUMPADDR and WAKEMAGIC, and branch to the address found there.
|
||||
*/
|
||||
dsb_sev();
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
smp_rmb();
|
||||
if (pen_release == -1)
|
||||
break;
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return pen_release != -1 ? -ENOSYS : 0;
|
||||
}
|
||||
|
||||
static void __init sirfsoc_smp_init_cpus(void)
|
||||
{
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
scu_enable(scu_base);
|
||||
}
|
||||
|
||||
struct smp_operations sirfsoc_smp_ops __initdata = {
|
||||
.smp_init_cpus = sirfsoc_smp_init_cpus,
|
||||
.smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
|
||||
.smp_secondary_init = sirfsoc_secondary_init,
|
||||
.smp_boot_secondary = sirfsoc_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = sirfsoc_cpu_die,
|
||||
#endif
|
||||
};
|
||||
@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
|
||||
|
||||
static struct of_device_id rstc_ids[] = {
|
||||
{ .compatible = "sirf,prima2-rstc" },
|
||||
{ .compatible = "sirf,marco-rstc" },
|
||||
{},
|
||||
};
|
||||
|
||||
@ -42,27 +43,37 @@ early_initcall(sirfsoc_of_rstc_init);
|
||||
|
||||
int sirfsoc_reset_device(struct device *dev)
|
||||
{
|
||||
const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
|
||||
unsigned int reset_bit;
|
||||
u32 reset_bit;
|
||||
|
||||
if (!prop)
|
||||
return -ENODEV;
|
||||
|
||||
reset_bit = be32_to_cpup(prop);
|
||||
if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&rstc_lock);
|
||||
|
||||
/*
|
||||
* Writing 1 to this bit resets corresponding block. Writing 0 to this
|
||||
* bit de-asserts reset signal of the corresponding block.
|
||||
* datasheet doesn't require explicit delay between the set and clear
|
||||
* of reset bit. it could be shorter if tests pass.
|
||||
*/
|
||||
writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
|
||||
sirfsoc_rstc_base + (reset_bit / 32) * 4);
|
||||
msleep(10);
|
||||
writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
|
||||
sirfsoc_rstc_base + (reset_bit / 32) * 4);
|
||||
if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
|
||||
/*
|
||||
* Writing 1 to this bit resets corresponding block. Writing 0 to this
|
||||
* bit de-asserts reset signal of the corresponding block.
|
||||
* datasheet doesn't require explicit delay between the set and clear
|
||||
* of reset bit. it could be shorter if tests pass.
|
||||
*/
|
||||
writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
|
||||
sirfsoc_rstc_base + (reset_bit / 32) * 4);
|
||||
msleep(10);
|
||||
writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
|
||||
sirfsoc_rstc_base + (reset_bit / 32) * 4);
|
||||
} else {
|
||||
/*
|
||||
* For MARCO and POLO
|
||||
* Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
|
||||
* register de-asserts reset signal of the corresponding block.
|
||||
* datasheet doesn't require explicit delay between the set and clear
|
||||
* of reset bit. it could be shorter if tests pass.
|
||||
*/
|
||||
writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
|
||||
msleep(10);
|
||||
writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
|
||||
}
|
||||
|
||||
mutex_unlock(&rstc_lock);
|
||||
|
||||
|
||||
@ -104,6 +104,7 @@ EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
|
||||
|
||||
static const struct of_device_id rtciobrg_ids[] = {
|
||||
{ .compatible = "sirf,prima2-rtciobg" },
|
||||
{ .compatible = "sirf,marco-rtciobg" },
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
316
arch/arm/mach-prima2/timer-marco.c
Normal file
316
arch/arm/mach-prima2/timer-marco.c
Normal file
@ -0,0 +1,316 @@
|
||||
/*
|
||||
* System timer for CSR SiRFprimaII
|
||||
*
|
||||
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <asm/sched_clock.h>
|
||||
#include <asm/localtimer.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
|
||||
#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
|
||||
#define SIRFSOC_TIMER_MATCH_0 0x0018
|
||||
#define SIRFSOC_TIMER_MATCH_1 0x001c
|
||||
#define SIRFSOC_TIMER_COUNTER_0 0x0048
|
||||
#define SIRFSOC_TIMER_COUNTER_1 0x004c
|
||||
#define SIRFSOC_TIMER_INTR_STATUS 0x0060
|
||||
#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
|
||||
#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
|
||||
#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
|
||||
#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
|
||||
#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
|
||||
#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
|
||||
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
|
||||
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
|
||||
|
||||
#define SIRFSOC_TIMER_REG_CNT 6
|
||||
|
||||
static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
|
||||
SIRFSOC_TIMER_WATCHDOG_EN,
|
||||
SIRFSOC_TIMER_32COUNTER_0_CTRL,
|
||||
SIRFSOC_TIMER_32COUNTER_1_CTRL,
|
||||
SIRFSOC_TIMER_64COUNTER_CTRL,
|
||||
SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
|
||||
SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
|
||||
};
|
||||
|
||||
static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
|
||||
|
||||
static void __iomem *sirfsoc_timer_base;
|
||||
static void __init sirfsoc_of_timer_map(void);
|
||||
|
||||
/* disable count and interrupt */
|
||||
static inline void sirfsoc_timer_count_disable(int idx)
|
||||
{
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
|
||||
}
|
||||
|
||||
/* enable count and interrupt */
|
||||
static inline void sirfsoc_timer_count_enable(int idx)
|
||||
{
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
|
||||
}
|
||||
|
||||
/* timer interrupt handler */
|
||||
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *ce = dev_id;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
/* clear timer interrupt */
|
||||
writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
|
||||
|
||||
if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
|
||||
sirfsoc_timer_count_disable(cpu);
|
||||
|
||||
ce->event_handler(ce);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* read 64-bit timer counter */
|
||||
static cycle_t sirfsoc_timer_read(struct clocksource *cs)
|
||||
{
|
||||
u64 cycles;
|
||||
|
||||
writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
|
||||
BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
|
||||
cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
|
||||
cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
|
||||
|
||||
return cycles;
|
||||
}
|
||||
|
||||
static int sirfsoc_timer_set_next_event(unsigned long delta,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
|
||||
4 * cpu);
|
||||
writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
|
||||
4 * cpu);
|
||||
|
||||
/* enable the tick */
|
||||
sirfsoc_timer_count_enable(cpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *ce)
|
||||
{
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
/* enable in set_next_event */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
sirfsoc_timer_count_disable(smp_processor_id());
|
||||
}
|
||||
|
||||
static void sirfsoc_clocksource_suspend(struct clocksource *cs)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
|
||||
sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
|
||||
}
|
||||
|
||||
static void sirfsoc_clocksource_resume(struct clocksource *cs)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
|
||||
writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
|
||||
|
||||
writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
|
||||
writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
|
||||
sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
|
||||
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
|
||||
BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
}
|
||||
|
||||
static struct clock_event_device sirfsoc_clockevent = {
|
||||
.name = "sirfsoc_clockevent",
|
||||
.rating = 200,
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = sirfsoc_timer_set_mode,
|
||||
.set_next_event = sirfsoc_timer_set_next_event,
|
||||
};
|
||||
|
||||
static struct clocksource sirfsoc_clocksource = {
|
||||
.name = "sirfsoc_clocksource",
|
||||
.rating = 200,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
.read = sirfsoc_timer_read,
|
||||
.suspend = sirfsoc_clocksource_suspend,
|
||||
.resume = sirfsoc_clocksource_resume,
|
||||
};
|
||||
|
||||
static struct irqaction sirfsoc_timer_irq = {
|
||||
.name = "sirfsoc_timer0",
|
||||
.flags = IRQF_TIMER | IRQF_NOBALANCING,
|
||||
.handler = sirfsoc_timer_interrupt,
|
||||
.dev_id = &sirfsoc_clockevent,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
|
||||
static struct irqaction sirfsoc_timer1_irq = {
|
||||
.name = "sirfsoc_timer1",
|
||||
.flags = IRQF_TIMER | IRQF_NOBALANCING,
|
||||
.handler = sirfsoc_timer_interrupt,
|
||||
};
|
||||
|
||||
static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
|
||||
{
|
||||
/* Use existing clock_event for cpu 0 */
|
||||
if (!smp_processor_id())
|
||||
return 0;
|
||||
|
||||
ce->irq = sirfsoc_timer1_irq.irq;
|
||||
ce->name = "local_timer";
|
||||
ce->features = sirfsoc_clockevent.features;
|
||||
ce->rating = sirfsoc_clockevent.rating;
|
||||
ce->set_mode = sirfsoc_timer_set_mode;
|
||||
ce->set_next_event = sirfsoc_timer_set_next_event;
|
||||
ce->shift = sirfsoc_clockevent.shift;
|
||||
ce->mult = sirfsoc_clockevent.mult;
|
||||
ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
|
||||
ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
|
||||
|
||||
sirfsoc_timer1_irq.dev_id = ce;
|
||||
BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
|
||||
irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
|
||||
|
||||
clockevents_register_device(ce);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
|
||||
{
|
||||
sirfsoc_timer_count_disable(1);
|
||||
|
||||
remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
|
||||
}
|
||||
|
||||
static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
|
||||
.setup = sirfsoc_local_timer_setup,
|
||||
.stop = sirfsoc_local_timer_stop,
|
||||
};
|
||||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
|
||||
static void __init sirfsoc_clockevent_init(void)
|
||||
{
|
||||
clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
|
||||
|
||||
sirfsoc_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(-2, &sirfsoc_clockevent);
|
||||
sirfsoc_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(2, &sirfsoc_clockevent);
|
||||
|
||||
sirfsoc_clockevent.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&sirfsoc_clockevent);
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
local_timer_register(&sirfsoc_local_timer_ops);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* initialize the kernel jiffy timer source */
|
||||
void __init sirfsoc_marco_timer_init(void)
|
||||
{
|
||||
unsigned long rate;
|
||||
u32 timer_div;
|
||||
struct clk *clk;
|
||||
|
||||
/* initialize clocking early, we want to set the OS timer */
|
||||
sirfsoc_of_clk_init();
|
||||
|
||||
/* timer's input clock is io clock */
|
||||
clk = clk_get_sys("io", NULL);
|
||||
|
||||
BUG_ON(IS_ERR(clk));
|
||||
rate = clk_get_rate(clk);
|
||||
|
||||
BUG_ON(rate < CLOCK_TICK_RATE);
|
||||
BUG_ON(rate % CLOCK_TICK_RATE);
|
||||
|
||||
sirfsoc_of_timer_map();
|
||||
|
||||
/* Initialize the timer dividers */
|
||||
timer_div = rate / CLOCK_TICK_RATE - 1;
|
||||
writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
|
||||
writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
|
||||
|
||||
/* Initialize timer counters to 0 */
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
|
||||
writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
|
||||
BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
|
||||
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
|
||||
|
||||
/* Clear all interrupts */
|
||||
writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
|
||||
|
||||
BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
|
||||
|
||||
BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
|
||||
|
||||
sirfsoc_clockevent_init();
|
||||
}
|
||||
|
||||
static struct of_device_id timer_ids[] = {
|
||||
{ .compatible = "sirf,marco-tick" },
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init sirfsoc_of_timer_map(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_matching_node(NULL, timer_ids);
|
||||
if (!np)
|
||||
return;
|
||||
sirfsoc_timer_base = of_iomap(np, 0);
|
||||
if (!sirfsoc_timer_base)
|
||||
panic("unable to map timer cpu registers\n");
|
||||
|
||||
sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
|
||||
if (!sirfsoc_timer_irq.irq)
|
||||
panic("No irq passed for timer0 via DT\n");
|
||||
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
|
||||
if (!sirfsoc_timer1_irq.irq)
|
||||
panic("No irq passed for timer1 via DT\n");
|
||||
#endif
|
||||
|
||||
of_node_put(np);
|
||||
}
|
||||
@ -181,7 +181,7 @@ static void __init sirfsoc_clockevent_init(void)
|
||||
}
|
||||
|
||||
/* initialize the kernel jiffy timer source */
|
||||
void __init sirfsoc_timer_init(void)
|
||||
void __init sirfsoc_prima2_timer_init(void)
|
||||
{
|
||||
unsigned long rate;
|
||||
struct clk *clk;
|
||||
@ -220,14 +220,14 @@ static struct of_device_id timer_ids[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
void __init sirfsoc_of_timer_map(void)
|
||||
static void __init sirfsoc_of_timer_map(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const unsigned int *intspec;
|
||||
|
||||
np = of_find_matching_node(NULL, timer_ids);
|
||||
if (!np)
|
||||
panic("unable to find compatible timer node in dtb\n");
|
||||
return;
|
||||
sirfsoc_timer_base = of_iomap(np, 0);
|
||||
if (!sirfsoc_timer_base)
|
||||
panic("unable to map timer cpu registers\n");
|
||||
Loading…
Reference in New Issue
Block a user