forked from Minki/linux
phy: qcom-ufs: add support for QUALCOMM Technologies UFS PHY drivers
This change adds a generic and common API support for ufs phy QUALCOMM Technologies. This support provides common code and also points to specific phy callbacks to differentiate between different behaviors of frequent use-cases (like power on, power off, phy calibration etc). Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
This commit is contained in:
Yaniv Gardi
Christoph Hellwig
parent
c7e09574d6
commit
adaafaa393
@ -277,4 +277,11 @@ config PHY_STIH41X_USB
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Enable this to support the USB transceiver that is part of
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STMicroelectronics STiH41x SoC series.
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config PHY_QCOM_UFS
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tristate "Qualcomm UFS PHY driver"
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depends on OF && ARCH_MSM
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select GENERIC_PHY
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help
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Support for UFS PHY on QCOM chipsets.
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endmenu
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@ -34,3 +34,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
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obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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118
drivers/phy/phy-qcom-ufs-i.h
Normal file
118
drivers/phy/phy-qcom-ufs-i.h
Normal file
@ -0,0 +1,118 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef UFS_QCOM_PHY_I_H_
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#define UFS_QCOM_PHY_I_H_
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#define UFS_QCOM_PHY_NAME_LEN 30
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struct ufs_qcom_phy_calibration {
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u32 reg_offset;
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u32 cfg_value;
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};
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struct ufs_qcom_phy_vreg {
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const char *name;
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struct regulator *reg;
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int max_uA;
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int min_uV;
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int max_uV;
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bool enabled;
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bool is_always_on;
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};
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struct ufs_qcom_phy {
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struct list_head list;
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struct device *dev;
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void __iomem *mmio;
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void __iomem *dev_ref_clk_ctrl_mmio;
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struct clk *tx_iface_clk;
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struct clk *rx_iface_clk;
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bool is_iface_clk_enabled;
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struct clk *ref_clk_src;
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struct clk *ref_clk_parent;
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struct clk *ref_clk;
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bool is_ref_clk_enabled;
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bool is_dev_ref_clk_enabled;
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struct ufs_qcom_phy_vreg vdda_pll;
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struct ufs_qcom_phy_vreg vdda_phy;
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struct ufs_qcom_phy_vreg vddp_ref_clk;
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unsigned int quirks;
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/*
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* If UFS link is put into Hibern8 and if UFS PHY analog hardware is
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* power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8
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* exit might fail even after powering on UFS PHY analog hardware.
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* Enabling this quirk will help to solve above issue by doing
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* custom PHY settings just before PHY analog power collapse.
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*/
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#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE BIT(0)
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u8 host_ctrl_rev_major;
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u16 host_ctrl_rev_minor;
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u16 host_ctrl_rev_step;
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char name[UFS_QCOM_PHY_NAME_LEN];
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struct ufs_qcom_phy_calibration *cached_regs;
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int cached_regs_table_size;
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bool is_powered_on;
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struct ufs_qcom_phy_specific_ops *phy_spec_ops;
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};
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/**
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* struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
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* specific implementation per phy. Each UFS phy, should implement
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* those functions according to its spec and requirements
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* @calibrate_phy: pointer to a function that calibrate the phy
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* @start_serdes: pointer to a function that starts the serdes
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* @is_physical_coding_sublayer_ready: pointer to a function that
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* checks pcs readiness. returns 0 for success and non-zero for error.
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* @set_tx_lane_enable: pointer to a function that enable tx lanes
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* @power_control: pointer to a function that controls analog rail of phy
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* and writes to QSERDES_RX_SIGDET_CNTRL attribute
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*/
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struct ufs_qcom_phy_specific_ops {
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int (*calibrate_phy)(struct ufs_qcom_phy *phy, bool is_rate_B);
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void (*start_serdes)(struct ufs_qcom_phy *phy);
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int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);
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void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);
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void (*power_control)(struct ufs_qcom_phy *phy, bool val);
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};
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struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);
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int ufs_qcom_phy_power_on(struct phy *generic_phy);
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int ufs_qcom_phy_power_off(struct phy *generic_phy);
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int ufs_qcom_phy_exit(struct phy *generic_phy);
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int ufs_qcom_phy_init_clks(struct phy *generic_phy,
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struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_init_vregulators(struct phy *generic_phy,
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struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_remove(struct phy *generic_phy,
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struct ufs_qcom_phy *ufs_qcom_phy);
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struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
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struct ufs_qcom_phy *common_cfg,
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struct phy_ops *ufs_qcom_phy_gen_ops,
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struct ufs_qcom_phy_specific_ops *phy_spec_ops);
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int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
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struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
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bool is_rate_B);
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#endif
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745
drivers/phy/phy-qcom-ufs.c
Normal file
745
drivers/phy/phy-qcom-ufs.c
Normal file
@ -0,0 +1,745 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "phy-qcom-ufs-i.h"
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#define MAX_PROP_NAME 32
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#define VDDA_PHY_MIN_UV 1000000
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#define VDDA_PHY_MAX_UV 1000000
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#define VDDA_PLL_MIN_UV 1800000
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#define VDDA_PLL_MAX_UV 1800000
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#define VDDP_REF_CLK_MIN_UV 1200000
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#define VDDP_REF_CLK_MAX_UV 1200000
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static int __ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *,
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const char *, bool);
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static int ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *,
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const char *);
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static int ufs_qcom_phy_base_init(struct platform_device *pdev,
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struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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struct ufs_qcom_phy_calibration *tbl_A,
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int tbl_size_A,
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struct ufs_qcom_phy_calibration *tbl_B,
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int tbl_size_B, bool is_rate_B)
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{
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int i;
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int ret = 0;
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if (!tbl_A) {
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dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
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ret = EINVAL;
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goto out;
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}
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for (i = 0; i < tbl_size_A; i++)
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writel_relaxed(tbl_A[i].cfg_value,
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ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
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/*
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* In case we would like to work in rate B, we need
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* to override a registers that were configured in rate A table
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* with registers of rate B table.
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* table.
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*/
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if (is_rate_B) {
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if (!tbl_B) {
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dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
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__func__);
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ret = EINVAL;
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goto out;
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}
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for (i = 0; i < tbl_size_B; i++)
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writel_relaxed(tbl_B[i].cfg_value,
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ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
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}
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/* flush buffered writes */
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mb();
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out:
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return ret;
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}
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struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
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struct ufs_qcom_phy *common_cfg,
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struct phy_ops *ufs_qcom_phy_gen_ops,
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struct ufs_qcom_phy_specific_ops *phy_spec_ops)
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{
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int err;
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struct device *dev = &pdev->dev;
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struct phy *generic_phy = NULL;
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struct phy_provider *phy_provider;
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err = ufs_qcom_phy_base_init(pdev, common_cfg);
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if (err) {
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dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
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goto out;
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}
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider)) {
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err = PTR_ERR(phy_provider);
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dev_err(dev, "%s: failed to register phy %d\n", __func__, err);
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goto out;
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}
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generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops);
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if (IS_ERR(generic_phy)) {
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err = PTR_ERR(generic_phy);
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dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
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goto out;
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}
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common_cfg->phy_spec_ops = phy_spec_ops;
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common_cfg->dev = dev;
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out:
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return generic_phy;
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}
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/*
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* This assumes the embedded phy structure inside generic_phy is of type
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* struct ufs_qcom_phy. In order to function properly it's crucial
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* to keep the embedded struct "struct ufs_qcom_phy common_cfg"
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* as the first inside generic_phy.
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*/
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struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
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{
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return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
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}
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static
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int ufs_qcom_phy_base_init(struct platform_device *pdev,
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struct ufs_qcom_phy *phy_common)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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int err = 0;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem");
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if (!res) {
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dev_err(dev, "%s: phy_mem resource not found\n", __func__);
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err = -ENOMEM;
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goto out;
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}
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phy_common->mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR((void const *)phy_common->mmio)) {
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err = PTR_ERR((void const *)phy_common->mmio);
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phy_common->mmio = NULL;
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dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n",
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__func__, err);
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goto out;
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}
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/* "dev_ref_clk_ctrl_mem" is optional resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"dev_ref_clk_ctrl_mem");
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if (!res) {
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dev_dbg(dev, "%s: dev_ref_clk_ctrl_mem resource not found\n",
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__func__);
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goto out;
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}
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phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio)) {
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err = PTR_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio);
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phy_common->dev_ref_clk_ctrl_mmio = NULL;
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dev_err(dev, "%s: ioremap for dev_ref_clk_ctrl_mem resource failed %d\n",
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__func__, err);
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}
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out:
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return err;
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}
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static int __ufs_qcom_phy_clk_get(struct phy *phy,
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const char *name, struct clk **clk_out, bool err_print)
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{
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struct clk *clk;
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int err = 0;
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
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struct device *dev = ufs_qcom_phy->dev;
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clk = devm_clk_get(dev, name);
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if (IS_ERR(clk)) {
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err = PTR_ERR(clk);
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if (err_print)
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dev_err(dev, "failed to get %s err %d", name, err);
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} else {
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*clk_out = clk;
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}
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return err;
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}
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static
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int ufs_qcom_phy_clk_get(struct phy *phy,
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const char *name, struct clk **clk_out)
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{
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return __ufs_qcom_phy_clk_get(phy, name, clk_out, true);
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}
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int
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ufs_qcom_phy_init_clks(struct phy *generic_phy,
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struct ufs_qcom_phy *phy_common)
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{
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int err;
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err = ufs_qcom_phy_clk_get(generic_phy, "tx_iface_clk",
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&phy_common->tx_iface_clk);
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if (err)
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goto out;
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err = ufs_qcom_phy_clk_get(generic_phy, "rx_iface_clk",
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&phy_common->rx_iface_clk);
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if (err)
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goto out;
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err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_src",
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&phy_common->ref_clk_src);
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if (err)
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goto out;
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/*
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* "ref_clk_parent" is optional hence don't abort init if it's not
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* found.
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*/
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__ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent",
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&phy_common->ref_clk_parent, false);
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err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk",
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&phy_common->ref_clk);
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out:
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return err;
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}
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int
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ufs_qcom_phy_init_vregulators(struct phy *generic_phy,
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struct ufs_qcom_phy *phy_common)
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{
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int err;
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err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_pll,
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"vdda-pll");
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if (err)
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goto out;
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err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_phy,
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"vdda-phy");
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if (err)
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goto out;
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/* vddp-ref-clk-* properties are optional */
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__ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vddp_ref_clk,
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"vddp-ref-clk", true);
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out:
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return err;
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}
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static int __ufs_qcom_phy_init_vreg(struct phy *phy,
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struct ufs_qcom_phy_vreg *vreg, const char *name, bool optional)
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{
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int err = 0;
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
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struct device *dev = ufs_qcom_phy->dev;
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char prop_name[MAX_PROP_NAME];
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vreg->name = kstrdup(name, GFP_KERNEL);
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if (!vreg->name) {
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err = -ENOMEM;
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goto out;
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}
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vreg->reg = devm_regulator_get(dev, name);
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if (IS_ERR(vreg->reg)) {
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err = PTR_ERR(vreg->reg);
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vreg->reg = NULL;
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if (!optional)
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dev_err(dev, "failed to get %s, %d\n", name, err);
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goto out;
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}
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if (dev->of_node) {
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snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name);
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err = of_property_read_u32(dev->of_node,
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prop_name, &vreg->max_uA);
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if (err && err != -EINVAL) {
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dev_err(dev, "%s: failed to read %s\n",
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__func__, prop_name);
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goto out;
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} else if (err == -EINVAL || !vreg->max_uA) {
|
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if (regulator_count_voltages(vreg->reg) > 0) {
|
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dev_err(dev, "%s: %s is mandatory\n",
|
||||
__func__, prop_name);
|
||||
goto out;
|
||||
}
|
||||
err = 0;
|
||||
}
|
||||
snprintf(prop_name, MAX_PROP_NAME, "%s-always-on", name);
|
||||
if (of_get_property(dev->of_node, prop_name, NULL))
|
||||
vreg->is_always_on = true;
|
||||
else
|
||||
vreg->is_always_on = false;
|
||||
}
|
||||
|
||||
if (!strcmp(name, "vdda-pll")) {
|
||||
vreg->max_uV = VDDA_PLL_MAX_UV;
|
||||
vreg->min_uV = VDDA_PLL_MIN_UV;
|
||||
} else if (!strcmp(name, "vdda-phy")) {
|
||||
vreg->max_uV = VDDA_PHY_MAX_UV;
|
||||
vreg->min_uV = VDDA_PHY_MIN_UV;
|
||||
} else if (!strcmp(name, "vddp-ref-clk")) {
|
||||
vreg->max_uV = VDDP_REF_CLK_MAX_UV;
|
||||
vreg->min_uV = VDDP_REF_CLK_MIN_UV;
|
||||
}
|
||||
|
||||
out:
|
||||
if (err)
|
||||
kfree(vreg->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int ufs_qcom_phy_init_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg, const char *name)
|
||||
{
|
||||
return __ufs_qcom_phy_init_vreg(phy, vreg, name, false);
|
||||
}
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_cfg_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg, bool on)
|
||||
{
|
||||
int ret = 0;
|
||||
struct regulator *reg = vreg->reg;
|
||||
const char *name = vreg->name;
|
||||
int min_uV;
|
||||
int uA_load;
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
|
||||
BUG_ON(!vreg);
|
||||
|
||||
if (regulator_count_voltages(reg) > 0) {
|
||||
min_uV = on ? vreg->min_uV : 0;
|
||||
ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: %s set voltage failed, err=%d\n",
|
||||
__func__, name, ret);
|
||||
goto out;
|
||||
}
|
||||
uA_load = on ? vreg->max_uA : 0;
|
||||
ret = regulator_set_optimum_mode(reg, uA_load);
|
||||
if (ret >= 0) {
|
||||
/*
|
||||
* regulator_set_optimum_mode() returns new regulator
|
||||
* mode upon success.
|
||||
*/
|
||||
ret = 0;
|
||||
} else {
|
||||
dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
|
||||
__func__, name, uA_load, ret);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_enable_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
int ret = 0;
|
||||
|
||||
if (!vreg || vreg->enabled)
|
||||
goto out;
|
||||
|
||||
ret = ufs_qcom_phy_cfg_vreg(phy, vreg, true);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = regulator_enable(vreg->reg);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: enable failed, err=%d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
vreg->enabled = true;
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
int ret = 0;
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->is_ref_clk_enabled)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* reference clock is propagated in a daisy-chained manner from
|
||||
* source to phy, so ungate them at each stage.
|
||||
*/
|
||||
ret = clk_prepare_enable(phy->ref_clk_src);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* "ref_clk_parent" is optional clock hence make sure that clk reference
|
||||
* is available before trying to enable the clock.
|
||||
*/
|
||||
if (phy->ref_clk_parent) {
|
||||
ret = clk_prepare_enable(phy->ref_clk_parent);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out_disable_src;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(phy->ref_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out_disable_parent;
|
||||
}
|
||||
|
||||
phy->is_ref_clk_enabled = true;
|
||||
goto out;
|
||||
|
||||
out_disable_parent:
|
||||
if (phy->ref_clk_parent)
|
||||
clk_disable_unprepare(phy->ref_clk_parent);
|
||||
out_disable_src:
|
||||
clk_disable_unprepare(phy->ref_clk_src);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static
|
||||
int ufs_qcom_phy_disable_vreg(struct phy *phy,
|
||||
struct ufs_qcom_phy_vreg *vreg)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
|
||||
struct device *dev = ufs_qcom_phy->dev;
|
||||
int ret = 0;
|
||||
|
||||
if (!vreg || !vreg->enabled || vreg->is_always_on)
|
||||
goto out;
|
||||
|
||||
ret = regulator_disable(vreg->reg);
|
||||
|
||||
if (!ret) {
|
||||
/* ignore errors on applying disable config */
|
||||
ufs_qcom_phy_cfg_vreg(phy, vreg, false);
|
||||
vreg->enabled = false;
|
||||
} else {
|
||||
dev_err(dev, "%s: %s disable failed, err=%d\n",
|
||||
__func__, vreg->name, ret);
|
||||
}
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->is_ref_clk_enabled) {
|
||||
clk_disable_unprepare(phy->ref_clk);
|
||||
/*
|
||||
* "ref_clk_parent" is optional clock hence make sure that clk
|
||||
* reference is available before trying to disable the clock.
|
||||
*/
|
||||
if (phy->ref_clk_parent)
|
||||
clk_disable_unprepare(phy->ref_clk_parent);
|
||||
clk_disable_unprepare(phy->ref_clk_src);
|
||||
phy->is_ref_clk_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
#define UFS_REF_CLK_EN (1 << 5)
|
||||
|
||||
static void ufs_qcom_phy_dev_ref_clk_ctrl(struct phy *generic_phy, bool enable)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->dev_ref_clk_ctrl_mmio &&
|
||||
(enable ^ phy->is_dev_ref_clk_enabled)) {
|
||||
u32 temp = readl_relaxed(phy->dev_ref_clk_ctrl_mmio);
|
||||
|
||||
if (enable)
|
||||
temp |= UFS_REF_CLK_EN;
|
||||
else
|
||||
temp &= ~UFS_REF_CLK_EN;
|
||||
|
||||
/*
|
||||
* If we are here to disable this clock immediately after
|
||||
* entering into hibern8, we need to make sure that device
|
||||
* ref_clk is active atleast 1us after the hibern8 enter.
|
||||
*/
|
||||
if (!enable)
|
||||
udelay(1);
|
||||
|
||||
writel_relaxed(temp, phy->dev_ref_clk_ctrl_mmio);
|
||||
/* ensure that ref_clk is enabled/disabled before we return */
|
||||
wmb();
|
||||
/*
|
||||
* If we call hibern8 exit after this, we need to make sure that
|
||||
* device ref_clk is stable for atleast 1us before the hibern8
|
||||
* exit command.
|
||||
*/
|
||||
if (enable)
|
||||
udelay(1);
|
||||
|
||||
phy->is_dev_ref_clk_enabled = enable;
|
||||
}
|
||||
}
|
||||
|
||||
void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true);
|
||||
}
|
||||
|
||||
void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy)
|
||||
{
|
||||
ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false);
|
||||
}
|
||||
|
||||
/* Turn ON M-PHY RMMI interface clocks */
|
||||
int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (phy->is_iface_clk_enabled)
|
||||
goto out;
|
||||
|
||||
ret = clk_prepare_enable(phy->tx_iface_clk);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
ret = clk_prepare_enable(phy->rx_iface_clk);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(phy->tx_iface_clk);
|
||||
dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
|
||||
__func__, ret);
|
||||
goto out;
|
||||
}
|
||||
phy->is_iface_clk_enabled = true;
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Turn OFF M-PHY RMMI interface clocks */
|
||||
void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (phy->is_iface_clk_enabled) {
|
||||
clk_disable_unprepare(phy->tx_iface_clk);
|
||||
clk_disable_unprepare(phy->rx_iface_clk);
|
||||
phy->is_iface_clk_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_start_serdes(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
|
||||
__func__);
|
||||
ret = -ENOTSUPP;
|
||||
} else {
|
||||
ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
|
||||
__func__);
|
||||
ret = -ENOTSUPP;
|
||||
} else {
|
||||
ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
|
||||
tx_lanes);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
|
||||
u8 major, u16 minor, u16 step)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
ufs_qcom_phy->host_ctrl_rev_major = major;
|
||||
ufs_qcom_phy->host_ctrl_rev_minor = minor;
|
||||
ufs_qcom_phy->host_ctrl_rev_step = step;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
int ret = 0;
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->calibrate_phy) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() callback is not supported\n",
|
||||
__func__);
|
||||
ret = -ENOTSUPP;
|
||||
} else {
|
||||
ret = ufs_qcom_phy->phy_spec_ops->
|
||||
calibrate_phy(ufs_qcom_phy, is_rate_B);
|
||||
if (ret)
|
||||
dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() failed %d\n",
|
||||
__func__, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_remove(struct phy *generic_phy,
|
||||
struct ufs_qcom_phy *ufs_qcom_phy)
|
||||
{
|
||||
phy_power_off(generic_phy);
|
||||
|
||||
kfree(ufs_qcom_phy->vdda_pll.name);
|
||||
kfree(ufs_qcom_phy->vdda_phy.name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_exit(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (ufs_qcom_phy->is_powered_on)
|
||||
phy_power_off(generic_phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
|
||||
dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
|
||||
__func__);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
return ufs_qcom_phy->phy_spec_ops->
|
||||
is_physical_coding_sublayer_ready(ufs_qcom_phy);
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_power_on(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
|
||||
struct device *dev = phy_common->dev;
|
||||
int err;
|
||||
|
||||
err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_phy);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
phy_common->phy_spec_ops->power_control(phy_common, true);
|
||||
|
||||
/* vdda_pll also enables ref clock LDOs so enable it first */
|
||||
err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_pll);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out_disable_phy;
|
||||
}
|
||||
|
||||
err = ufs_qcom_phy_enable_ref_clk(generic_phy);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out_disable_pll;
|
||||
}
|
||||
|
||||
/* enable device PHY ref_clk pad rail */
|
||||
if (phy_common->vddp_ref_clk.reg) {
|
||||
err = ufs_qcom_phy_enable_vreg(generic_phy,
|
||||
&phy_common->vddp_ref_clk);
|
||||
if (err) {
|
||||
dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n",
|
||||
__func__, err);
|
||||
goto out_disable_ref_clk;
|
||||
}
|
||||
}
|
||||
|
||||
phy_common->is_powered_on = true;
|
||||
goto out;
|
||||
|
||||
out_disable_ref_clk:
|
||||
ufs_qcom_phy_disable_ref_clk(generic_phy);
|
||||
out_disable_pll:
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
|
||||
out_disable_phy:
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
||||
int ufs_qcom_phy_power_off(struct phy *generic_phy)
|
||||
{
|
||||
struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
|
||||
|
||||
phy_common->phy_spec_ops->power_control(phy_common, false);
|
||||
|
||||
if (phy_common->vddp_ref_clk.reg)
|
||||
ufs_qcom_phy_disable_vreg(generic_phy,
|
||||
&phy_common->vddp_ref_clk);
|
||||
ufs_qcom_phy_disable_ref_clk(generic_phy);
|
||||
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
|
||||
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
|
||||
phy_common->is_powered_on = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user