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drm/radeon: enable SRBM timeout interrupt on EG/NI

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Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2015-02-18 13:19:28 +01:00 committed by Alex Deucher
parent 18ad01effe
commit acc1522a54
4 changed files with 17 additions and 0 deletions
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7
drivers/gpu/drm/radeon/evergreen.c
View File

@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
} }
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
WREG32(SRBM_INT_CNTL, 0x1);
WREG32(SRBM_INT_ACK, 0x1);
evergreen_fix_pci_max_read_req_size(rdev); evergreen_fix_pci_max_read_req_size(rdev);
@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
WREG32(DMA_CNTL, tmp); WREG32(DMA_CNTL, tmp);
WREG32(GRBM_INT_CNTL, 0); WREG32(GRBM_INT_CNTL, 0);
WREG32(SRBM_INT_CNTL, 0);
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
if (rdev->num_crtc >= 4) { if (rdev->num_crtc >= 4) {
@ -5066,6 +5069,10 @@ restart_ih:
DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
break; break;
} }
case 96:
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
WREG32(SRBM_INT_ACK, 0x1);
break;
case 124: /* UVD */ case 124: /* UVD */
DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);

4
drivers/gpu/drm/radeon/evergreend.h
View File

@ -1191,6 +1191,10 @@
#define SOFT_RESET_REGBB (1 << 22) #define SOFT_RESET_REGBB (1 << 22)
#define SOFT_RESET_ORB (1 << 23) #define SOFT_RESET_ORB (1 << 23)
#define SRBM_READ_ERROR 0xE98
#define SRBM_INT_CNTL 0xEA0
#define SRBM_INT_ACK 0xEA8
/* display watermarks */ /* display watermarks */
#define DC_LB_MEMORY_SPLIT 0x6b0c #define DC_LB_MEMORY_SPLIT 0x6b0c
#define PRIORITY_A_CNT 0x6b18 #define PRIORITY_A_CNT 0x6b18

2
drivers/gpu/drm/radeon/ni.c
View File

@ -962,6 +962,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
} }
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
WREG32(SRBM_INT_CNTL, 0x1);
WREG32(SRBM_INT_ACK, 0x1);
evergreen_fix_pci_max_read_req_size(rdev); evergreen_fix_pci_max_read_req_size(rdev);

4
drivers/gpu/drm/radeon/nid.h
View File

@ -82,6 +82,10 @@
#define SOFT_RESET_REGBB (1 << 22) #define SOFT_RESET_REGBB (1 << 22)
#define SOFT_RESET_ORB (1 << 23) #define SOFT_RESET_ORB (1 << 23)
#define SRBM_READ_ERROR 0xE98
#define SRBM_INT_CNTL 0xEA0
#define SRBM_INT_ACK 0xEA8
#define SRBM_STATUS2 0x0EC4 #define SRBM_STATUS2 0x0EC4
#define DMA_BUSY (1 << 5) #define DMA_BUSY (1 << 5)
#define DMA1_BUSY (1 << 6) #define DMA1_BUSY (1 << 6)