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drm/i915: Add IVB DDB partitioning control

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On IVB the display data buffer partitioning control lives in the
DISP_ARB_CTL2 register. Add the relevant defines/code for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-12-05 15:51:28 +02:00 committed by Daniel Vetter
parent 243eaf381d
commit ac9545fda6
2 changed files with 24 additions and 8 deletions
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2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4148,6 +4148,8 @@
#define DISP_ARB_CTL 0x45000 #define DISP_ARB_CTL 0x45000
#define DISP_TILE_SURFACE_SWIZZLING (1<<13) #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
#define DISP_FBC_WM_DIS (1<<15) #define DISP_FBC_WM_DIS (1<<15)
#define DISP_ARB_CTL2 0x45004
#define DISP_DATA_PARTITION_5_6 (1<<6)
#define GEN7_MSG_CTL 0x45010 #define GEN7_MSG_CTL 0x45010
#define WAIT_FOR_PCH_RESET_ACK (1<<1) #define WAIT_FOR_PCH_RESET_ACK (1<<1)
#define WAIT_FOR_PCH_FLR_ACK (1<<0) #define WAIT_FOR_PCH_FLR_ACK (1<<0)

30
drivers/gpu/drm/i915/intel_pm.c
View File

@ -2864,6 +2864,7 @@ static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
static void hsw_write_wm_values(struct drm_i915_private *dev_priv, static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
struct hsw_wm_values *results) struct hsw_wm_values *results)
{ {
struct drm_device *dev = dev_priv->dev;
struct hsw_wm_values *previous = &dev_priv->wm.hw; struct hsw_wm_values *previous = &dev_priv->wm.hw;
unsigned int dirty; unsigned int dirty;
uint32_t val; uint32_t val;
@ -2894,12 +2895,21 @@ static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
if (dirty & WM_DIRTY_DDB) { if (dirty & WM_DIRTY_DDB) {
val = I915_READ(WM_MISC); if (IS_HASWELL(dev)) {
if (results->partitioning == INTEL_DDB_PART_1_2) val = I915_READ(WM_MISC);
val &= ~WM_MISC_DATA_PARTITION_5_6; if (results->partitioning == INTEL_DDB_PART_1_2)
else val &= ~WM_MISC_DATA_PARTITION_5_6;
val |= WM_MISC_DATA_PARTITION_5_6; else
I915_WRITE(WM_MISC, val); val |= WM_MISC_DATA_PARTITION_5_6;
I915_WRITE(WM_MISC, val);
} else {
val = I915_READ(DISP_ARB_CTL2);
if (results->partitioning == INTEL_DDB_PART_1_2)
val &= ~DISP_DATA_PARTITION_5_6;
else
val |= DISP_DATA_PARTITION_5_6;
I915_WRITE(DISP_ARB_CTL2, val);
}
} }
if (dirty & WM_DIRTY_FBC) { if (dirty & WM_DIRTY_FBC) {
@ -3210,8 +3220,12 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? if (IS_HASWELL(dev))
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
else if (IS_IVYBRIDGE(dev))
hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
hw->enable_fbc_wm = hw->enable_fbc_wm =
!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);