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clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

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The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.

This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.

Cc: stable@vger.kernel.org
Fixes: 2ab836db50 ("clk: sunxi-ng: Add M-P factor clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2017-02-14 11:35:22 +08:00 committed by Maxime Ripard
parent c1ae3cfa0e
commit ac8616e4c8
1 changed files with 8 additions and 0 deletions
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8
drivers/clk/sunxi-ng/ccu_mp.c
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@ -85,6 +85,10 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
unsigned int m, p;
u32 reg;
/* Adjust parent_rate according to pre-dividers */
ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
-1, &parent_rate);
reg = readl(cmp->common.base + cmp->common.reg);
m = reg >> cmp->m.shift;
@ -117,6 +121,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned int m, p;
u32 reg;
/* Adjust parent_rate according to pre-dividers */
ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
-1, &parent_rate);
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);