Merge branches 'clock_fixes_3.4rc', 'clockdomain_fixes_3.4rc', 'hsmmc_erratum_2_1_1_128_refine_3.4rc1', 'hwmod_data_fixes_a_3.4rc', 'hwmod_fixes_a2_3.4rc' and 'powerdomain_fixes_a_3.4rc' into omap-fixes-a2-for-3.4rc-branch
This commit is contained in:
commit
a9dd31b744
@ -390,7 +390,7 @@ static struct clockdomain emu_sys_44xx_clkdm = {
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.cm_inst = OMAP4430_PRM_EMU_CM_INST,
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.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
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.flags = CLKDM_CAN_HWSUP,
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.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
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};
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static struct clockdomain l3_dma_44xx_clkdm = {
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@ -506,6 +506,13 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
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if (oh->dev_attr != NULL) {
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mmc_dev_attr = oh->dev_attr;
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mmc_data->controller_flags = mmc_dev_attr->flags;
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/*
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* erratum 2.1.1.128 doesn't apply if board has
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* a transceiver is attached
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*/
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if (hsmmcinfo->transceiver)
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mmc_data->controller_flags &=
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~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
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}
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pdev = platform_device_alloc(name, ctrl_nr - 1);
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@ -1477,6 +1477,11 @@ static int _reset(struct omap_hwmod *oh)
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ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
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if (oh->class->sysc) {
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_update_sysc_cache(oh);
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_enable_sysc(oh);
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}
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return ret;
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}
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@ -1786,20 +1791,9 @@ static int _setup(struct omap_hwmod *oh, void *data)
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return 0;
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}
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if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
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if (!(oh->flags & HWMOD_INIT_NO_RESET))
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_reset(oh);
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/*
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* OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
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* The _enable() function should be split to
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* avoid the rewrite of the OCP_SYSCONFIG register.
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*/
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if (oh->class->sysc) {
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_update_sysc_cache(oh);
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_enable_sysc(oh);
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}
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}
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postsetup_state = oh->_postsetup_state;
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if (postsetup_state == _HWMOD_STATE_UNKNOWN)
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postsetup_state = _HWMOD_STATE_ENABLED;
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@ -1907,20 +1901,10 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
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*/
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int omap_hwmod_softreset(struct omap_hwmod *oh)
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{
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u32 v;
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int ret;
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if (!oh || !(oh->_sysc_cache))
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if (!oh)
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return -EINVAL;
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v = oh->_sysc_cache;
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ret = _set_softreset(oh, &v);
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if (ret)
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goto error;
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_write_sysconfig(v, oh);
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error:
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return ret;
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return _ocp_softreset(oh);
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}
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/**
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@ -2463,26 +2447,28 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
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* @oh: struct omap_hwmod *
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*
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* Sets the module OCP socket ENAWAKEUP bit to allow the module to
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* send wakeups to the PRCM. Eventually this should sets PRCM wakeup
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* registers to cause the PRCM to receive wakeup events from the
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* module. Does not set any wakeup routing registers beyond this
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* point - if the module is to wake up any other module or subsystem,
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* that must be set separately. Called by omap_device code. Returns
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* -EINVAL on error or 0 upon success.
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* send wakeups to the PRCM, and enable I/O ring wakeup events for
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* this IP block if it has dynamic mux entries. Eventually this
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* should set PRCM wakeup registers to cause the PRCM to receive
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* wakeup events from the module. Does not set any wakeup routing
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* registers beyond this point - if the module is to wake up any other
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* module or subsystem, that must be set separately. Called by
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* omap_device code. Returns -EINVAL on error or 0 upon success.
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*/
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int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
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{
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unsigned long flags;
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u32 v;
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if (!oh->class->sysc ||
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!(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
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return -EINVAL;
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spin_lock_irqsave(&oh->_lock, flags);
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v = oh->_sysc_cache;
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_enable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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if (oh->class->sysc &&
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(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
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v = oh->_sysc_cache;
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_enable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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}
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_set_idle_ioring_wakeup(oh, true);
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spin_unlock_irqrestore(&oh->_lock, flags);
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@ -2494,26 +2480,28 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
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* @oh: struct omap_hwmod *
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*
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* Clears the module OCP socket ENAWAKEUP bit to prevent the module
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* from sending wakeups to the PRCM. Eventually this should clear
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* PRCM wakeup registers to cause the PRCM to ignore wakeup events
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* from the module. Does not set any wakeup routing registers beyond
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* this point - if the module is to wake up any other module or
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* subsystem, that must be set separately. Called by omap_device
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* code. Returns -EINVAL on error or 0 upon success.
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* from sending wakeups to the PRCM, and disable I/O ring wakeup
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* events for this IP block if it has dynamic mux entries. Eventually
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* this should clear PRCM wakeup registers to cause the PRCM to ignore
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* wakeup events from the module. Does not set any wakeup routing
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* registers beyond this point - if the module is to wake up any other
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* module or subsystem, that must be set separately. Called by
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* omap_device code. Returns -EINVAL on error or 0 upon success.
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*/
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int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
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{
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unsigned long flags;
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u32 v;
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if (!oh->class->sysc ||
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!(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
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return -EINVAL;
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spin_lock_irqsave(&oh->_lock, flags);
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v = oh->_sysc_cache;
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_disable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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if (oh->class->sysc &&
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(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
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v = oh->_sysc_cache;
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_disable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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}
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_set_idle_ioring_wakeup(oh, false);
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spin_unlock_irqrestore(&oh->_lock, flags);
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@ -2996,6 +2996,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
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&omap44xx_l4_abe__mcbsp1_dma,
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};
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static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
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{ .role = "pad_fck", .clk = "pad_clks_ck" },
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{ .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
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};
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static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
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.name = "mcbsp1",
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.class = &omap44xx_mcbsp_hwmod_class,
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@ -3012,6 +3017,8 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
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},
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.slaves = omap44xx_mcbsp1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
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.opt_clks = mcbsp1_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
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};
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/* mcbsp2 */
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@ -3071,6 +3078,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
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&omap44xx_l4_abe__mcbsp2_dma,
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};
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static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
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{ .role = "pad_fck", .clk = "pad_clks_ck" },
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{ .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
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};
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static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
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.name = "mcbsp2",
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.class = &omap44xx_mcbsp_hwmod_class,
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@ -3087,6 +3099,8 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
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},
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.slaves = omap44xx_mcbsp2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
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.opt_clks = mcbsp2_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
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};
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/* mcbsp3 */
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@ -3146,6 +3160,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
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&omap44xx_l4_abe__mcbsp3_dma,
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};
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static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
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{ .role = "pad_fck", .clk = "pad_clks_ck" },
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{ .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
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};
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static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
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.name = "mcbsp3",
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.class = &omap44xx_mcbsp_hwmod_class,
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@ -3162,6 +3181,8 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
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},
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.slaves = omap44xx_mcbsp3_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
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.opt_clks = mcbsp3_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
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};
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/* mcbsp4 */
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@ -3200,6 +3221,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
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&omap44xx_l4_per__mcbsp4,
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};
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static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
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{ .role = "pad_fck", .clk = "pad_clks_ck" },
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{ .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
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};
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static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
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.name = "mcbsp4",
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.class = &omap44xx_mcbsp_hwmod_class,
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@ -3216,6 +3242,8 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
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},
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.slaves = omap44xx_mcbsp4_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
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.opt_clks = mcbsp4_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
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};
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/*
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@ -972,7 +972,13 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
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int pwrdm_state_switch(struct powerdomain *pwrdm)
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{
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return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
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int ret;
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ret = pwrdm_wait_transition(pwrdm);
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if (!ret)
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ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
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return ret;
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}
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int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
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@ -47,17 +47,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
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* with the original PRCM protocol defined for OMAP2420
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*/
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#define SYSC_TYPE1_MIDLEMODE_SHIFT 12
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#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
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#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
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#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
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#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
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#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
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#define SYSC_TYPE1_SIDLEMODE_SHIFT 3
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#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
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#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
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#define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
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#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
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#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
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#define SYSC_TYPE1_SOFTRESET_SHIFT 1
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#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
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#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
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#define SYSC_TYPE1_AUTOIDLE_SHIFT 0
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#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
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#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
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/*
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* OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
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