musb: am35x: fix compile error due to control apis
commit 4814ced511 (OMAP:
control: move plat-omap/control.h to mach-omap2/control.h)
moved <plat/control.h> to another location, preventing
drivers from accessing it, so we need to pass function
pointers from arch code to be able to talk to internal
PHY on AM35x.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Ajay Kumar Gupta
Felipe Balbi
parent
46960847ef
commit
a9c037832e
@ -30,9 +30,102 @@
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#include <mach/irqs.h>
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#include <mach/am35xx.h>
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#include <plat/usb.h>
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#include "control.h"
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#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
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static void am35x_musb_reset(void)
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{
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u32 regval;
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/* Reset the musb interface */
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regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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regval |= AM35XX_USBOTGSS_SW_RST;
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omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
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regval &= ~AM35XX_USBOTGSS_SW_RST;
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omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
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regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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}
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static void am35x_musb_phy_power(u8 on)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(100);
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u32 devconf2;
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if (on) {
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/*
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* Start the on-chip PHY and its PLL.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
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devconf2 |= CONF2_PHY_PLLON;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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pr_info(KERN_INFO "Waiting for PHY clock good...\n");
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while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
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& CONF2_PHYCLKGD)) {
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cpu_relax();
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if (time_after(jiffies, timeout)) {
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pr_err(KERN_ERR "musb PHY clock good timed out\n");
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break;
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}
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}
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} else {
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/*
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* Power down the on-chip PHY.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~CONF2_PHY_PLLON;
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devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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}
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}
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static void am35x_musb_clear_irq(void)
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{
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u32 regval;
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regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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regval |= AM35XX_USBOTGSS_INT_CLR;
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omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
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regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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}
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static void am35x_musb_set_mode(u8 musb_mode)
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{
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u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~CONF2_OTGMODE;
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switch (musb_mode) {
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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case MUSB_HOST: /* Force VBUS valid, ID = 0 */
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devconf2 |= CONF2_FORCE_HOST;
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break;
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#endif
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#ifdef CONFIG_USB_GADGET_MUSB_HDRC
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case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
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devconf2 |= CONF2_FORCE_DEVICE;
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break;
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#endif
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#ifdef CONFIG_USB_MUSB_OTG
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case MUSB_OTG: /* Don't override the VBUS/ID comparators */
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devconf2 |= CONF2_NO_OVERRIDE;
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break;
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#endif
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default:
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pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
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}
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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}
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static struct resource musb_resources[] = {
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[0] = { /* start and end set dynamically */
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.flags = IORESOURCE_MEM,
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@ -96,6 +189,10 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
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musb_device.name = "musb-am35x";
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musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;
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musb_resources[1].start = INT_35XX_USBOTG_IRQ;
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board_data->set_phy_power = am35x_musb_phy_power;
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board_data->clear_irq = am35x_musb_clear_irq;
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board_data->set_mode = am35x_musb_set_mode;
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board_data->reset = am35x_musb_reset;
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} else if (cpu_is_omap34xx()) {
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musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
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} else if (cpu_is_omap44xx()) {
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@ -70,6 +70,10 @@ struct omap_musb_board_data {
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u8 mode;
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u16 power;
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unsigned extvbus:1;
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void (*set_phy_power)(u8 on);
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void (*clear_irq)(void);
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void (*set_mode)(u8 mode);
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void (*reset)(void);
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};
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enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
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@ -32,7 +32,6 @@
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <plat/control.h>
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#include <plat/usb.h>
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#include "musb_core.h"
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@ -90,47 +89,6 @@ struct am35x_glue {
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};
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#define glue_to_musb(g) platform_get_drvdata(g->musb)
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static inline void phy_on(void)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(100);
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u32 devconf2;
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/*
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* Start the on-chip PHY and its PLL.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
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devconf2 |= CONF2_PHY_PLLON;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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DBG(1, "Waiting for PHY clock good...\n");
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while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
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& CONF2_PHYCLKGD)) {
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cpu_relax();
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if (time_after(jiffies, timeout)) {
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DBG(1, "musb PHY clock good timed out\n");
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break;
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}
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}
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}
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static inline void phy_off(void)
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{
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u32 devconf2;
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/*
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* Power down the on-chip PHY.
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*/
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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devconf2 &= ~CONF2_PHY_PLLON;
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devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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}
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/*
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* am35x_musb_enable - enable interrupts
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*/
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@ -265,9 +223,12 @@ static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
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{
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struct musb *musb = hci;
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void __iomem *reg_base = musb->ctrl_base;
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struct device *dev = musb->controller;
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struct musb_hdrc_platform_data *plat = dev->platform_data;
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struct omap_musb_board_data *data = plat->board_data;
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unsigned long flags;
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irqreturn_t ret = IRQ_NONE;
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u32 epintr, usbintr, lvl_intr;
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u32 epintr, usbintr;
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spin_lock_irqsave(&musb->lock, flags);
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@ -356,9 +317,8 @@ eoi:
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/* EOI needs to be written for the IRQ to be re-asserted. */
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if (ret == IRQ_HANDLED || epintr || usbintr) {
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/* clear level interrupt */
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lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
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omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
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if (data->clear_irq)
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data->clear_irq();
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/* write EOI */
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musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
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}
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@ -374,37 +334,26 @@ eoi:
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static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
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{
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u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
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struct device *dev = musb->controller;
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struct musb_hdrc_platform_data *plat = dev->platform_data;
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struct omap_musb_board_data *data = plat->board_data;
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int retval = 0;
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devconf2 &= ~CONF2_OTGMODE;
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switch (musb_mode) {
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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case MUSB_HOST: /* Force VBUS valid, ID = 0 */
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devconf2 |= CONF2_FORCE_HOST;
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break;
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#endif
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#ifdef CONFIG_USB_GADGET_MUSB_HDRC
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case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
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devconf2 |= CONF2_FORCE_DEVICE;
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break;
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#endif
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#ifdef CONFIG_USB_MUSB_OTG
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case MUSB_OTG: /* Don't override the VBUS/ID comparators */
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devconf2 |= CONF2_NO_OVERRIDE;
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break;
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#endif
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default:
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DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
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}
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if (data->set_mode)
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data->set_mode(musb_mode);
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else
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retval = -EIO;
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
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return 0;
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return retval;
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}
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static int am35x_musb_init(struct musb *musb)
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{
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struct device *dev = musb->controller;
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struct musb_hdrc_platform_data *plat = dev->platform_data;
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struct omap_musb_board_data *data = plat->board_data;
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void __iomem *reg_base = musb->ctrl_base;
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u32 rev, lvl_intr, sw_reset;
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u32 rev;
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musb->mregs += USB_MENTOR_CORE_OFFSET;
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@ -421,39 +370,40 @@ static int am35x_musb_init(struct musb *musb)
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if (is_host_enabled(musb))
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setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
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/* Global reset */
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sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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sw_reset |= AM35XX_USBOTGSS_SW_RST;
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omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
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sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
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omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
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/* Reset the musb */
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if (data->reset)
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data->reset();
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/* Reset the controller */
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musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
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/* Start the on-chip PHY and its PLL. */
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phy_on();
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if (data->set_phy_power)
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data->set_phy_power(1);
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msleep(5);
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musb->isr = am35x_musb_interrupt;
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/* clear level interrupt */
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lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
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omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
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if (data->clear_irq)
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data->clear_irq();
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return 0;
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}
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static int am35x_musb_exit(struct musb *musb)
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{
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struct device *dev = musb->controller;
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struct musb_hdrc_platform_data *plat = dev->platform_data;
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struct omap_musb_board_data *data = plat->board_data;
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if (is_host_enabled(musb))
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del_timer_sync(&otg_workaround);
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phy_off();
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/* Shutdown the on-chip PHY and its PLL. */
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if (data->set_phy_power)
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data->set_phy_power(0);
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otg_put_transceiver(musb->xceiv);
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usb_nop_xceiv_unregister();
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@ -630,8 +580,13 @@ static int __exit am35x_remove(struct platform_device *pdev)
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static int am35x_suspend(struct device *dev)
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{
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struct am35x_glue *glue = dev_get_drvdata(dev);
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struct musb_hdrc_platform_data *plat = dev->platform_data;
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struct omap_musb_board_data *data = plat->board_data;
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/* Shutdown the on-chip PHY and its PLL. */
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if (data->set_phy_power)
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data->set_phy_power(0);
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phy_off();
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clk_disable(glue->phy_clk);
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clk_disable(glue->clk);
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@ -641,9 +596,14 @@ static int am35x_suspend(struct device *dev)
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static int am35x_resume(struct device *dev)
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{
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struct am35x_glue *glue = dev_get_drvdata(dev);
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struct musb_hdrc_platform_data *plat = dev->platform_data;
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struct omap_musb_board_data *data = plat->board_data;
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int ret;
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phy_on();
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/* Start the on-chip PHY and its PLL. */
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if (data->set_phy_power)
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data->set_phy_power(1);
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ret = clk_enable(glue->phy_clk);
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if (ret) {
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dev_err(dev, "failed to enable PHY clock\n");
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