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dt-bindings: clock: Add bindings for Exynos850 sysreg clocks

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System Register is used to configure system behavior, like USI protocol,
etc. SYSREG clocks should be provided to corresponding syscon nodes, to
make it possible to modify SYSREG registers.

While at it, add also missing PMU and GPIO clocks, which looks necessary
and might be needed for corresponding Exynos850 features soon.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211217161549.24836-2-semen.protsenko@linaro.org
This commit is contained in:
Sam Protsenko 2021-12-17 18:15:43 +02:00 committed by Sylwester Nawrocki
parent bcda841f9b
commit a949f2cf1a
1 changed files with 9 additions and 3 deletions
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12
include/dt-bindings/clock/exynos850.h
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@ -82,7 +82,10 @@
#define CLK_GOUT_I3C_PCLK 19 #define CLK_GOUT_I3C_PCLK 19
#define CLK_GOUT_I3C_SCLK 20 #define CLK_GOUT_I3C_SCLK 20
#define CLK_GOUT_SPEEDY_PCLK 21 #define CLK_GOUT_SPEEDY_PCLK 21
#define APM_NR_CLK 22 #define CLK_GOUT_GPIO_ALIVE_PCLK 22
#define CLK_GOUT_PMU_ALIVE_PCLK 23
#define CLK_GOUT_SYSREG_APM_PCLK 24
#define APM_NR_CLK 25
/* CMU_CMGP */ /* CMU_CMGP */
#define CLK_RCO_CMGP 1 #define CLK_RCO_CMGP 1
@ -99,7 +102,8 @@
#define CLK_GOUT_CMGP_USI0_PCLK 12 #define CLK_GOUT_CMGP_USI0_PCLK 12
#define CLK_GOUT_CMGP_USI1_IPCLK 13 #define CLK_GOUT_CMGP_USI1_IPCLK 13
#define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_CMGP_USI1_PCLK 14
#define CMGP_NR_CLK 15 #define CLK_GOUT_SYSREG_CMGP_PCLK 15
#define CMGP_NR_CLK 16
/* CMU_HSI */ /* CMU_HSI */
#define CLK_MOUT_HSI_BUS_USER 1 #define CLK_MOUT_HSI_BUS_USER 1
@ -167,7 +171,9 @@
#define CLK_GOUT_MMC_EMBD_SDCLKIN 10 #define CLK_GOUT_MMC_EMBD_SDCLKIN 10
#define CLK_GOUT_SSS_ACLK 11 #define CLK_GOUT_SSS_ACLK 11
#define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_SSS_PCLK 12
#define CORE_NR_CLK 13 #define CLK_GOUT_GPIO_CORE_PCLK 13
#define CLK_GOUT_SYSREG_CORE_PCLK 14
#define CORE_NR_CLK 15
/* CMU_DPU */ /* CMU_DPU */
#define CLK_MOUT_DPU_USER 1 #define CLK_MOUT_DPU_USER 1