forked from Minki/linux
cpuidle: Convert Qualcomm SPM driver to a generic CPUidle driver
The Qualcomm SPM cpuidle driver seems to be the last driver still
using the generic ARM CPUidle infrastructure.
Converting it actually allows us to simplify the driver,
and we end up being able to remove more lines than adding new ones:
- We can parse the CPUidle states in the device tree directly
with dt_idle_states (and don't need to duplicate that
functionality into the spm driver).
- Each "saw" device managed by the SPM driver now directly
registers its own cpuidle driver, removing the need for
any global (per cpu) state.
The device tree binding is the same, so the driver stays
compatible with all old device trees.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Lina Iyer <ilina@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Stephan Gerhold
Rafael J. Wysocki
parent
a0bd8a2780
commit
a871be6b8e
@ -2225,6 +2225,7 @@ F: drivers/*/qcom*
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F: drivers/*/qcom/
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F: drivers/bluetooth/btqcomsmd.c
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F: drivers/clocksource/timer-qcom.c
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F: drivers/cpuidle/cpuidle-qcom-spm.c
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F: drivers/extcon/extcon-qcom*
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F: drivers/i2c/busses/i2c-qcom-geni.c
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F: drivers/i2c/busses/i2c-qup.c
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@ -94,3 +94,16 @@ config ARM_TEGRA_CPUIDLE
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select ARM_CPU_SUSPEND
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help
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Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs.
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config ARM_QCOM_SPM_CPUIDLE
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bool "CPU Idle Driver for Qualcomm Subsystem Power Manager (SPM)"
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depends on (ARCH_QCOM || COMPILE_TEST) && !ARM64
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select ARM_CPU_SUSPEND
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select CPU_IDLE_MULTIPLE_DRIVERS
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select DT_IDLE_STATES
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select QCOM_SCM
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help
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Select this to enable cpuidle for Qualcomm processors.
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The Subsystem Power Manager (SPM) controls low power modes for the
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CPU and L2 cores. It interface with various system drivers to put
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the cores in low power modes.
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@ -25,6 +25,7 @@ obj-$(CONFIG_ARM_PSCI_CPUIDLE) += cpuidle_psci.o
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cpuidle_psci-y := cpuidle-psci.o
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cpuidle_psci-$(CONFIG_PM_GENERIC_DOMAINS_OF) += cpuidle-psci-domain.o
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obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o
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obj-$(CONFIG_ARM_QCOM_SPM_CPUIDLE) += cpuidle-qcom-spm.o
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###############################################################################
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# MIPS drivers
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@ -19,10 +19,11 @@
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#include <linux/cpu_pm.h>
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#include <linux/qcom_scm.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include "dt_idle_states.h"
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#define MAX_PMIC_DATA 2
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#define MAX_SEQ_DATA 64
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#define SPM_CTL_INDEX 0x7f
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@ -62,6 +63,7 @@ struct spm_reg_data {
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};
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struct spm_driver_data {
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struct cpuidle_driver cpuidle_driver;
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void __iomem *reg_base;
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const struct spm_reg_data *reg_data;
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};
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@ -107,11 +109,6 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
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typedef int (*idle_fn)(void);
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static DEFINE_PER_CPU(idle_fn*, qcom_idle_ops);
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static inline void spm_register_write(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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@ -172,10 +169,9 @@ static int qcom_pm_collapse(unsigned long int unused)
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return -1;
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}
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static int qcom_cpu_spc(void)
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static int qcom_cpu_spc(struct spm_driver_data *drv)
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{
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int ret;
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struct spm_driver_data *drv = __this_cpu_read(cpu_spm_drv);
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
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ret = cpu_suspend(0, qcom_pm_collapse);
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@ -190,94 +186,49 @@ static int qcom_cpu_spc(void)
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return ret;
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}
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static int qcom_idle_enter(unsigned long index)
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static int spm_enter_idle_state(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int idx)
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{
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return __this_cpu_read(qcom_idle_ops)[index]();
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struct spm_driver_data *data = container_of(drv, struct spm_driver_data,
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cpuidle_driver);
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return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data);
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}
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static const struct of_device_id qcom_idle_state_match[] __initconst = {
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{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
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static struct cpuidle_driver qcom_spm_idle_driver = {
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.name = "qcom_spm",
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.owner = THIS_MODULE,
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.states[0] = {
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.enter = spm_enter_idle_state,
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.exit_latency = 1,
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.target_residency = 1,
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.power_usage = UINT_MAX,
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.name = "WFI",
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.desc = "ARM WFI",
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}
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};
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static const struct of_device_id qcom_idle_state_match[] = {
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{ .compatible = "qcom,idle-state-spc", .data = spm_enter_idle_state },
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{ },
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};
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static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
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static int spm_cpuidle_init(struct cpuidle_driver *drv, int cpu)
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{
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const struct of_device_id *match_id;
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struct device_node *state_node;
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int i;
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int state_count = 1;
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idle_fn idle_fns[CPUIDLE_STATE_MAX];
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idle_fn *fns;
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cpumask_t mask;
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bool use_scm_power_down = false;
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int ret;
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if (!qcom_scm_is_available())
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return -EPROBE_DEFER;
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memcpy(drv, &qcom_spm_idle_driver, sizeof(*drv));
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drv->cpumask = (struct cpumask *)cpumask_of(cpu);
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for (i = 0; ; i++) {
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state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
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if (!state_node)
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break;
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/* Parse idle states from device tree */
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ret = dt_init_idle_driver(drv, qcom_idle_state_match, 1);
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if (ret <= 0)
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return ret ? : -ENODEV;
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if (!of_device_is_available(state_node))
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continue;
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if (i == CPUIDLE_STATE_MAX) {
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pr_warn("%s: cpuidle states reached max possible\n",
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__func__);
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break;
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}
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match_id = of_match_node(qcom_idle_state_match, state_node);
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if (!match_id)
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return -ENODEV;
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idle_fns[state_count] = match_id->data;
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/* Check if any of the states allow power down */
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if (match_id->data == qcom_cpu_spc)
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use_scm_power_down = true;
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state_count++;
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}
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if (state_count == 1)
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goto check_spm;
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fns = devm_kcalloc(get_cpu_device(cpu), state_count, sizeof(*fns),
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GFP_KERNEL);
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if (!fns)
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return -ENOMEM;
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for (i = 1; i < state_count; i++)
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fns[i] = idle_fns[i];
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if (use_scm_power_down) {
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/* We have atleast one power down mode */
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cpumask_clear(&mask);
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cpumask_set_cpu(cpu, &mask);
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qcom_scm_set_warm_boot_addr(cpu_resume_arm, &mask);
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}
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per_cpu(qcom_idle_ops, cpu) = fns;
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/*
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* SPM probe for the cpu should have happened by now, if the
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* SPM device does not exist, return -ENXIO to indicate that the
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* cpu does not support idle states.
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*/
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check_spm:
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return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENXIO;
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/* We have atleast one power down mode */
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return qcom_scm_set_warm_boot_addr(cpu_resume_arm, drv->cpumask);
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}
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static const struct cpuidle_ops qcom_cpuidle_ops __initconst = {
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.suspend = qcom_idle_enter,
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.init = qcom_cpuidle_init,
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};
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CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v1, "qcom,kpss-acc-v1", &qcom_cpuidle_ops);
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CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v2, "qcom,kpss-acc-v2", &qcom_cpuidle_ops);
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static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
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int *spm_cpu)
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{
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@ -323,11 +274,15 @@ static int spm_dev_probe(struct platform_device *pdev)
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struct resource *res;
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const struct of_device_id *match_id;
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void __iomem *addr;
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int cpu;
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int cpu, ret;
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if (!qcom_scm_is_available())
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return -EPROBE_DEFER;
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drv = spm_get_drv(pdev, &cpu);
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if (!drv)
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return -EINVAL;
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platform_set_drvdata(pdev, drv);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
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@ -340,6 +295,10 @@ static int spm_dev_probe(struct platform_device *pdev)
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drv->reg_data = match_id->data;
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ret = spm_cpuidle_init(&drv->cpuidle_driver, cpu);
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if (ret)
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return ret;
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/* Write the SPM sequences first.. */
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addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
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__iowrite32_copy(addr, drv->reg_data->seq,
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@ -362,13 +321,20 @@ static int spm_dev_probe(struct platform_device *pdev)
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/* Set up Standby as the default low power mode */
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
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per_cpu(cpu_spm_drv, cpu) = drv;
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return cpuidle_register(&drv->cpuidle_driver, NULL);
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}
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static int spm_dev_remove(struct platform_device *pdev)
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{
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struct spm_driver_data *drv = platform_get_drvdata(pdev);
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cpuidle_unregister(&drv->cpuidle_driver);
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return 0;
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}
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static struct platform_driver spm_driver = {
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.probe = spm_dev_probe,
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.remove = spm_dev_remove,
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.driver = {
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.name = "saw",
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.of_match_table = spm_match_table,
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@ -80,16 +80,6 @@ config QCOM_PDR_HELPERS
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tristate
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select QCOM_QMI_HELPERS
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config QCOM_PM
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bool "Qualcomm Power Management"
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depends on ARCH_QCOM && !ARM64
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select ARM_CPU_SUSPEND
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select QCOM_SCM
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help
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QCOM Platform specific power driver to manage cores and L2 low power
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modes. It interface with various system drivers to put the cores in
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low power modes.
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config QCOM_QMI_HELPERS
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tristate
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depends on NET
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@ -8,7 +8,6 @@ obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
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obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
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obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
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obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
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obj-$(CONFIG_QCOM_PM) += spm.o
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obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o
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qmi_helpers-y += qmi_encdec.o qmi_interface.o
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obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o
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