forked from Minki/linux
The imx cleanup for 3.10:
* Clean up a couple of unneeded function declarations * Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well as the replacement * Remove platform ahci support * Clean up unused ARCH/MACH Kconfig symbols * Remove a couple of unused files -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRZBpzAAoJEFBXWFqHsHzOfyAH/RdvhORI0rNhBAOrSxleWlMy AMP9x6G5tXNK/fgtxopvCiS4VXw5MB01uqJWMVM9+hx6676oCXWc/L3I6iT5l87B qPY/e9LyGJa5aOYczPuUT2sG+Ga8989GhOksA+L6kWHZ2df0BIB9rBRZnoPezEAx u2ATdioyzfj2rAnDNFOxsw6oai265mowt/f8J/7EQfxgkAMcKov7/BpVac0po55R tv+Hr3T7OBg3p/h5PYi5iAehVCToCKOD31QpnlhS+dmKS52w7tEO6T75INt7HzC8 CJT0zi5jJ3/tDJsdYJ1SS4MHK4U43y0oV7cw7sO7TzNreyOB6bzTWDqhdJY2oMM= =N7xl -----END PGP SIGNATURE----- Merge tag 'imx-cleanup-3.10' into imx/soc The imx cleanup for 3.10: * Clean up a couple of unneeded function declarations * Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well as the replacement * Remove platform ahci support * Clean up unused ARCH/MACH Kconfig symbols * Remove a couple of unused files
This commit is contained in:
Shawn Guo
commit
a862d88d3f
@ -2163,13 +2163,6 @@ if ARCH_HAS_CPUFREQ
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source "drivers/cpufreq/Kconfig"
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config CPU_FREQ_IMX
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tristate "CPUfreq driver for i.MX CPUs"
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depends on ARCH_MXC && CPU_FREQ
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select CPU_FREQ_TABLE
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help
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This enables the CPUfreq driver for i.MX CPUs.
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config CPU_FREQ_SA1100
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bool
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@ -83,24 +83,12 @@ config ARCH_MXC_IOMUX_V3
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config ARCH_MX1
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bool
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config MACH_MX21
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bool
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config ARCH_MX25
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bool
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config MACH_MX27
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bool
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config ARCH_MX5
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bool
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config ARCH_MX51
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bool
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config ARCH_MX53
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bool
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config SOC_IMX1
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bool
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select ARCH_MX1
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@ -114,7 +102,6 @@ config SOC_IMX21
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select COMMON_CLK
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select CPU_ARM926T
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select IMX_HAVE_IOMUX_V1
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select MACH_MX21
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select MXC_AVIC
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config SOC_IMX25
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@ -155,7 +142,6 @@ config SOC_IMX35
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config SOC_IMX5
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bool
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select ARCH_HAS_CPUFREQ
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select ARCH_MX5
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select ARCH_MXC_IOMUX_V3
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select COMMON_CLK
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select CPU_V7
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@ -163,8 +149,6 @@ config SOC_IMX5
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config SOC_IMX51
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bool
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select ARCH_MX5
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select ARCH_MX51
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select PINCTRL
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select PINCTRL_IMX51
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select SOC_IMX5
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@ -789,8 +773,6 @@ comment "Device tree only"
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config SOC_IMX53
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bool "i.MX53 support"
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select ARCH_MX5
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select ARCH_MX53
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select HAVE_CAN_FLEXCAN if CAN
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select PINCTRL
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@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
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obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
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imx5-pm-$(CONFIG_PM) += pm-imx5.o
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obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
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obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
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obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
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clk-pfd.o clk-busy.o clk.o
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@ -27,7 +27,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
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obj-$(CONFIG_MXC_ULPI) += ulpi.o
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obj-$(CONFIG_MXC_USE_EPIT) += epit.o
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obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
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obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-y += cpuidle.o
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@ -1,35 +0,0 @@
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zreladdr-$(CONFIG_SOC_IMX1) += 0x08008000
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params_phys-$(CONFIG_SOC_IMX1) := 0x08000100
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initrd_phys-$(CONFIG_SOC_IMX1) := 0x08800000
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zreladdr-$(CONFIG_SOC_IMX21) += 0xC0008000
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params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100
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initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000
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zreladdr-$(CONFIG_SOC_IMX25) += 0x80008000
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params_phys-$(CONFIG_SOC_IMX25) := 0x80000100
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initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000
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zreladdr-$(CONFIG_SOC_IMX27) += 0xA0008000
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params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100
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initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000
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zreladdr-$(CONFIG_SOC_IMX31) += 0x80008000
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params_phys-$(CONFIG_SOC_IMX31) := 0x80000100
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initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000
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zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
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params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
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initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
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zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
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params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
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initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
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zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000
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params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
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initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
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zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
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params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
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initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
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@ -54,8 +54,6 @@
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void __iomem *avic_base;
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static struct irq_domain *domain;
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static u32 avic_saved_mask_reg[2];
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#ifdef CONFIG_MXC_IRQ_PRIOR
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static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
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{
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@ -113,6 +111,8 @@ static struct mxc_extra_irq avic_extra_irq = {
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};
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#ifdef CONFIG_PM
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static u32 avic_saved_mask_reg[2];
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static void avic_irq_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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@ -278,8 +278,6 @@ int __init mx27_clocks_init(unsigned long fref)
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clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
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clk_register_clkdev(clk[cpu_div], "cpu", NULL);
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clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
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clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
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clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
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mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
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@ -113,7 +113,6 @@ extern void imx_set_cpu_jump(int cpu, void *jump_addr);
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extern u32 imx_get_cpu_arg(int cpu);
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extern void imx_set_cpu_arg(int cpu, u32 arg);
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extern void v7_cpu_resume(void);
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extern u32 *pl310_get_save_ptr(void);
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#ifdef CONFIG_SMP
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extern void v7_secondary_startup(void);
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extern void imx_scu_map_io(void);
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@ -124,8 +123,6 @@ static inline void imx_scu_map_io(void) {}
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static inline void imx_smp_prepare(void) {}
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static inline void imx_scu_standby_enable(void) {}
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#endif
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extern void imx_enable_cpu(int cpu, bool enable);
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extern void imx_set_cpu_jump(int cpu, void *jump_addr);
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extern void imx_src_init(void);
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extern void imx_src_prepare_restart(void);
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extern void imx_gpc_init(void);
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@ -1,31 +0,0 @@
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/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/bug.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include "hardware.h"
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static struct cpu_op mx51_cpu_op[] = {
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{
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.cpu_rate = 160000000,},
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{
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.cpu_rate = 800000000,},
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};
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struct cpu_op *mx51_get_cpu_op(int *op)
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{
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*op = ARRAY_SIZE(mx51_cpu_op);
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return mx51_cpu_op;
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}
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@ -1,14 +0,0 @@
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/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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extern struct cpu_op *mx51_get_cpu_op(int *op);
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@ -1,206 +0,0 @@
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/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*
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* A driver for the Freescale Semiconductor i.MXC CPUfreq module.
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* The CPUFREQ driver is for controlling CPU frequency. It allows you to change
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* the CPU clock speed on the fly.
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*/
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#include <linux/module.h>
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#include <linux/cpufreq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include "hardware.h"
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#define CLK32_FREQ 32768
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#define NANOSECOND (1000 * 1000 * 1000)
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struct cpu_op *(*get_cpu_op)(int *op);
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static int cpu_freq_khz_min;
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static int cpu_freq_khz_max;
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static struct clk *cpu_clk;
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static struct cpufreq_frequency_table *imx_freq_table;
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static int cpu_op_nr;
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static struct cpu_op *cpu_op_tbl;
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static int set_cpu_freq(int freq)
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{
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int ret = 0;
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int org_cpu_rate;
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org_cpu_rate = clk_get_rate(cpu_clk);
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if (org_cpu_rate == freq)
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return ret;
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ret = clk_set_rate(cpu_clk, freq);
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if (ret != 0) {
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printk(KERN_DEBUG "cannot set CPU clock rate\n");
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return ret;
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}
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return ret;
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}
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static int mxc_verify_speed(struct cpufreq_policy *policy)
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{
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if (policy->cpu != 0)
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return -EINVAL;
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return cpufreq_frequency_table_verify(policy, imx_freq_table);
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}
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static unsigned int mxc_get_speed(unsigned int cpu)
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{
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if (cpu)
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return 0;
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return clk_get_rate(cpu_clk) / 1000;
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}
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static int mxc_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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struct cpufreq_freqs freqs;
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int freq_Hz;
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int ret = 0;
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unsigned int index;
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|
||||
cpufreq_frequency_table_target(policy, imx_freq_table,
|
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target_freq, relation, &index);
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freq_Hz = imx_freq_table[index].frequency * 1000;
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||||
|
||||
freqs.old = clk_get_rate(cpu_clk) / 1000;
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freqs.new = freq_Hz / 1000;
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freqs.cpu = 0;
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||||
freqs.flags = 0;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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|
||||
ret = set_cpu_freq(freq_Hz);
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||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxc_cpufreq_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
printk(KERN_INFO "i.MXC CPU frequency driver\n");
|
||||
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (!get_cpu_op)
|
||||
return -EINVAL;
|
||||
|
||||
cpu_clk = clk_get(NULL, "cpu_clk");
|
||||
if (IS_ERR(cpu_clk)) {
|
||||
printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
|
||||
return PTR_ERR(cpu_clk);
|
||||
}
|
||||
|
||||
cpu_op_tbl = get_cpu_op(&cpu_op_nr);
|
||||
|
||||
cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
|
||||
cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
|
||||
|
||||
imx_freq_table = kmalloc(
|
||||
sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
|
||||
GFP_KERNEL);
|
||||
if (!imx_freq_table) {
|
||||
ret = -ENOMEM;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
for (i = 0; i < cpu_op_nr; i++) {
|
||||
imx_freq_table[i].index = i;
|
||||
imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
|
||||
if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
|
||||
cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
|
||||
if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
|
||||
cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
}
|
||||
|
||||
imx_freq_table[i].index = i;
|
||||
imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
policy->cur = clk_get_rate(cpu_clk) / 1000;
|
||||
policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
|
||||
policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
|
||||
|
||||
/* Manual states, that PLL stabilizes in two CLK32 periods */
|
||||
policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
|
||||
|
||||
ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
|
||||
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
|
||||
__func__, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
|
||||
return 0;
|
||||
err:
|
||||
kfree(imx_freq_table);
|
||||
err1:
|
||||
clk_put(cpu_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
|
||||
{
|
||||
cpufreq_frequency_table_put_attr(policy->cpu);
|
||||
|
||||
set_cpu_freq(cpu_freq_khz_max * 1000);
|
||||
clk_put(cpu_clk);
|
||||
kfree(imx_freq_table);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct cpufreq_driver mxc_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = mxc_verify_speed,
|
||||
.target = mxc_set_target,
|
||||
.get = mxc_get_speed,
|
||||
.init = mxc_cpufreq_init,
|
||||
.exit = mxc_cpufreq_exit,
|
||||
.name = "imx",
|
||||
};
|
||||
|
||||
static int mxc_cpufreq_driver_init(void)
|
||||
{
|
||||
return cpufreq_register_driver(&mxc_driver);
|
||||
}
|
||||
|
||||
static void mxc_cpufreq_driver_exit(void)
|
||||
{
|
||||
cpufreq_unregister_driver(&mxc_driver);
|
||||
}
|
||||
|
||||
module_init(mxc_cpufreq_driver_init);
|
||||
module_exit(mxc_cpufreq_driver_exit);
|
||||
|
||||
MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
|
||||
MODULE_DESCRIPTION("CPUfreq driver for i.MX");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -86,7 +86,3 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
||||
|
||||
config IMX_HAVE_PLATFORM_SPI_IMX
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_AHCI
|
||||
bool
|
||||
default y if ARCH_MX53
|
||||
|
||||
@ -29,5 +29,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
|
||||
|
||||
@ -344,13 +344,3 @@ struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
|
||||
int irq, int irq_err);
|
||||
struct platform_device *imx_add_imx_sdma(char *name,
|
||||
resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
|
||||
|
||||
#include <linux/ahci_platform.h>
|
||||
struct imx_ahci_imx_data {
|
||||
const char *devid;
|
||||
resource_size_t iobase;
|
||||
resource_size_t irq;
|
||||
};
|
||||
struct platform_device *__init imx_add_ahci_imx(
|
||||
const struct imx_ahci_imx_data *data,
|
||||
const struct ahci_platform_data *pdata);
|
||||
|
||||
@ -1,157 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include "../hardware.h"
|
||||
#include "devices-common.h"
|
||||
|
||||
#define imx_ahci_imx_data_entry_single(soc, _devid) \
|
||||
{ \
|
||||
.devid = _devid, \
|
||||
.iobase = soc ## _SATA_BASE_ADDR, \
|
||||
.irq = soc ## _INT_SATA, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
|
||||
imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
|
||||
#endif
|
||||
|
||||
enum {
|
||||
HOST_CAP = 0x00,
|
||||
HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
|
||||
HOST_PORTS_IMPL = 0x0c,
|
||||
HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
|
||||
};
|
||||
|
||||
static struct clk *sata_clk, *sata_ref_clk;
|
||||
|
||||
/* AHCI module Initialization, if return 0, initialization is successful. */
|
||||
static int imx_sata_init(struct device *dev, void __iomem *addr)
|
||||
{
|
||||
u32 tmpdata;
|
||||
int ret = 0;
|
||||
struct clk *clk;
|
||||
|
||||
sata_clk = clk_get(dev, "ahci");
|
||||
if (IS_ERR(sata_clk)) {
|
||||
dev_err(dev, "no sata clock.\n");
|
||||
return PTR_ERR(sata_clk);
|
||||
}
|
||||
ret = clk_prepare_enable(sata_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't prepare/enable sata clock.\n");
|
||||
goto put_sata_clk;
|
||||
}
|
||||
|
||||
/* Get the AHCI SATA PHY CLK */
|
||||
sata_ref_clk = clk_get(dev, "ahci_phy");
|
||||
if (IS_ERR(sata_ref_clk)) {
|
||||
dev_err(dev, "no sata ref clock.\n");
|
||||
ret = PTR_ERR(sata_ref_clk);
|
||||
goto release_sata_clk;
|
||||
}
|
||||
ret = clk_prepare_enable(sata_ref_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't prepare/enable sata ref clock.\n");
|
||||
goto put_sata_ref_clk;
|
||||
}
|
||||
|
||||
/* Get the AHB clock rate, and configure the TIMER1MS reg later */
|
||||
clk = clk_get(dev, "ahci_dma");
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(dev, "no dma clock.\n");
|
||||
ret = PTR_ERR(clk);
|
||||
goto release_sata_ref_clk;
|
||||
}
|
||||
tmpdata = clk_get_rate(clk) / 1000;
|
||||
clk_put(clk);
|
||||
|
||||
writel(tmpdata, addr + HOST_TIMER1MS);
|
||||
|
||||
tmpdata = readl(addr + HOST_CAP);
|
||||
if (!(tmpdata & HOST_CAP_SSS)) {
|
||||
tmpdata |= HOST_CAP_SSS;
|
||||
writel(tmpdata, addr + HOST_CAP);
|
||||
}
|
||||
|
||||
if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
|
||||
writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
|
||||
addr + HOST_PORTS_IMPL);
|
||||
|
||||
return 0;
|
||||
|
||||
release_sata_ref_clk:
|
||||
clk_disable_unprepare(sata_ref_clk);
|
||||
put_sata_ref_clk:
|
||||
clk_put(sata_ref_clk);
|
||||
release_sata_clk:
|
||||
clk_disable_unprepare(sata_clk);
|
||||
put_sata_clk:
|
||||
clk_put(sata_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void imx_sata_exit(struct device *dev)
|
||||
{
|
||||
clk_disable_unprepare(sata_ref_clk);
|
||||
clk_put(sata_ref_clk);
|
||||
|
||||
clk_disable_unprepare(sata_clk);
|
||||
clk_put(sata_clk);
|
||||
|
||||
}
|
||||
struct platform_device *__init imx_add_ahci_imx(
|
||||
const struct imx_ahci_imx_data *data,
|
||||
const struct ahci_platform_data *pdata)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = data->iobase,
|
||||
.end = data->iobase + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = data->irq,
|
||||
.end = data->irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
return imx_add_platform_device_dmamask(data->devid, 0,
|
||||
res, ARRAY_SIZE(res),
|
||||
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
|
||||
}
|
||||
|
||||
struct platform_device *__init imx53_add_ahci_imx(void)
|
||||
{
|
||||
struct ahci_platform_data pdata = {
|
||||
.init = imx_sata_init,
|
||||
.exit = imx_sata_exit,
|
||||
};
|
||||
|
||||
return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
|
||||
}
|
||||
@ -102,7 +102,6 @@
|
||||
|
||||
#include "mxc.h"
|
||||
|
||||
#include "mx6q.h"
|
||||
#include "mx51.h"
|
||||
#include "mx53.h"
|
||||
#include "mx3x.h"
|
||||
|
||||
@ -33,7 +33,6 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx51.h"
|
||||
#include "cpu_op-mx51.h"
|
||||
#include "eukrea-baseboards.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx51.h"
|
||||
@ -285,10 +284,6 @@ static void __init eukrea_cpuimx51sd_init(void)
|
||||
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
|
||||
ARRAY_SIZE(eukrea_cpuimx51sd_pads));
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ_IMX)
|
||||
get_cpu_op = mx51_get_cpu_op;
|
||||
#endif
|
||||
|
||||
imx51_add_imx_uart(0, &uart_pdata);
|
||||
imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
|
||||
imx51_add_imx2_wdt(0);
|
||||
|
||||
@ -27,7 +27,6 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx51.h"
|
||||
#include "cpu_op-mx51.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx51.h"
|
||||
|
||||
@ -371,9 +370,6 @@ static void __init mx51_babbage_init(void)
|
||||
|
||||
imx51_soc_init();
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ_IMX)
|
||||
get_cpu_op = mx51_get_cpu_op;
|
||||
#endif
|
||||
imx51_babbage_common_init();
|
||||
|
||||
imx51_add_imx_uart(0, &uart_pdata);
|
||||
|
||||
@ -1,31 +0,0 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __MACH_MX6Q_H__
|
||||
#define __MACH_MX6Q_H__
|
||||
|
||||
#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
|
||||
#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
|
||||
|
||||
/*
|
||||
* The following are the blocks that need to be statically mapped.
|
||||
* For other blocks, the base address really should be retrieved from
|
||||
* device tree.
|
||||
*/
|
||||
#define MX6Q_SCU_BASE_ADDR 0x00a00000
|
||||
#define MX6Q_SCU_SIZE 0x1000
|
||||
#define MX6Q_CCM_BASE_ADDR 0x020c4000
|
||||
#define MX6Q_CCM_SIZE 0x4000
|
||||
#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
|
||||
#define MX6Q_ANATOP_SIZE 0x1000
|
||||
|
||||
#endif /* __MACH_MX6Q_H__ */
|
||||
Loading…
Reference in New Issue
Block a user