forked from Minki/linux
AMD IOMMU: add MSI interrupt support
The AMD IOMMU can generate interrupts for various reasons. This patch adds the basic interrupt enabling infrastructure to the driver. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Joerg Roedel
Ingo Molnar
parent
3eaf28a1cd
commit
a80dc3e0e0
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@ -553,6 +553,7 @@ config CALGARY_IOMMU_ENABLED_BY_DEFAULT
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config AMD_IOMMU
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bool "AMD IOMMU support"
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select SWIOTLB
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select PCI_MSI
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depends on X86_64 && PCI && ACPI
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help
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With this option you can enable support for AMD IOMMU hardware in
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@ -49,6 +49,17 @@ static int iommu_has_npcache(struct amd_iommu *iommu)
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return iommu->cap & IOMMU_CAP_NPCACHE;
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}
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/****************************************************************************
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*
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* Interrupt handling functions
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*
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****************************************************************************/
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irqreturn_t amd_iommu_int_handler(int irq, void *data)
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{
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return IRQ_NONE;
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}
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/****************************************************************************
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*
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* IOMMU command queuing functions
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@ -22,6 +22,8 @@
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#include <linux/gfp.h>
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#include <linux/list.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/msi.h>
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#include <asm/pci-direct.h>
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#include <asm/amd_iommu_types.h>
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#include <asm/amd_iommu.h>
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@ -515,17 +517,20 @@ static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
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static void __init init_iommu_from_pci(struct amd_iommu *iommu)
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{
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int cap_ptr = iommu->cap_ptr;
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u32 range;
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u32 range, misc;
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pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
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&iommu->cap);
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pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
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&range);
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pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
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&misc);
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iommu->first_device = calc_devid(MMIO_GET_BUS(range),
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MMIO_GET_FD(range));
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iommu->last_device = calc_devid(MMIO_GET_BUS(range),
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MMIO_GET_LD(range));
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iommu->evt_msi_num = MMIO_MSI_NUM(misc);
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}
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/*
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@ -696,6 +701,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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if (!iommu->evt_buf)
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return -ENOMEM;
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iommu->int_enabled = false;
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init_iommu_from_pci(iommu);
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init_iommu_from_acpi(iommu, h);
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init_iommu_devices(iommu);
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@ -741,6 +748,95 @@ static int __init init_iommu_all(struct acpi_table_header *table)
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return 0;
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}
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/****************************************************************************
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*
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* The following functions initialize the MSI interrupts for all IOMMUs
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* in the system. Its a bit challenging because there could be multiple
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* IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
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* pci_dev.
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*
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****************************************************************************/
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static int __init iommu_setup_msix(struct amd_iommu *iommu)
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{
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struct amd_iommu *curr;
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struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */
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int nvec = 0, i;
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list_for_each_entry(curr, &amd_iommu_list, list) {
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if (curr->dev == iommu->dev) {
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entries[nvec].entry = curr->evt_msi_num;
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entries[nvec].vector = 0;
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curr->int_enabled = true;
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nvec++;
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}
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}
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if (pci_enable_msix(iommu->dev, entries, nvec)) {
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pci_disable_msix(iommu->dev);
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return 1;
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}
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for (i = 0; i < nvec; ++i) {
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int r = request_irq(entries->vector, amd_iommu_int_handler,
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IRQF_SAMPLE_RANDOM,
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"AMD IOMMU",
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NULL);
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if (r)
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goto out_free;
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}
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return 0;
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out_free:
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for (i -= 1; i >= 0; --i)
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free_irq(entries->vector, NULL);
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pci_disable_msix(iommu->dev);
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return 1;
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}
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static int __init iommu_setup_msi(struct amd_iommu *iommu)
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{
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int r;
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struct amd_iommu *curr;
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list_for_each_entry(curr, &amd_iommu_list, list) {
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if (curr->dev == iommu->dev)
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curr->int_enabled = true;
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}
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if (pci_enable_msi(iommu->dev))
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return 1;
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r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
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IRQF_SAMPLE_RANDOM,
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"AMD IOMMU",
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NULL);
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if (r) {
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pci_disable_msi(iommu->dev);
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return 1;
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}
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return 0;
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}
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static int __init iommu_init_msi(struct amd_iommu *iommu)
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{
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if (iommu->int_enabled)
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return 0;
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if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX))
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return iommu_setup_msix(iommu);
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else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
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return iommu_setup_msi(iommu);
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return 1;
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}
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/****************************************************************************
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*
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* The next functions belong to the third pass of parsing the ACPI
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@ -862,6 +958,7 @@ static void __init enable_iommus(void)
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list_for_each_entry(iommu, &amd_iommu_list, list) {
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iommu_set_exclusion_range(iommu);
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iommu_init_msi(iommu);
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iommu_enable(iommu);
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}
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}
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@ -20,10 +20,13 @@
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#ifndef _ASM_X86_AMD_IOMMU_H
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#define _ASM_X86_AMD_IOMMU_H
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#include <linux/irqreturn.h>
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#ifdef CONFIG_AMD_IOMMU
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extern int amd_iommu_init(void);
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extern int amd_iommu_init_dma_ops(void);
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extern void amd_iommu_detect(void);
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extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
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#else
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static inline int amd_iommu_init(void) { return -ENODEV; }
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static inline void amd_iommu_detect(void) { }
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@ -37,6 +37,7 @@
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/* Capability offsets used by the driver */
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#define MMIO_CAP_HDR_OFFSET 0x00
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#define MMIO_RANGE_OFFSET 0x0c
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#define MMIO_MISC_OFFSET 0x10
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/* Masks, shifts and macros to parse the device range capability */
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#define MMIO_RANGE_LD_MASK 0xff000000
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@ -48,6 +49,7 @@
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#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
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#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
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#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
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#define MMIO_MSI_NUM(x) ((x) & 0x1f)
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/* Flag masks for the AMD IOMMU exclusion range */
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#define MMIO_EXCL_ENABLE_MASK 0x01ULL
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@ -255,10 +257,15 @@ struct amd_iommu {
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u8 *evt_buf;
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/* size of event buffer */
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u32 evt_buf_size;
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/* MSI number for event interrupt */
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u16 evt_msi_num;
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/* if one, we need to send a completion wait command */
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int need_sync;
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/* true if interrupts for this IOMMU are already enabled */
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bool int_enabled;
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/* default dma_ops domain for that IOMMU */
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struct dma_ops_domain *default_dom;
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};
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