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drm/i915: Fix Ironlake M/N/P ranges to match the spec

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Without this fix, some modes couldn't find appropriate clocks.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Matthew Garrett <mjg@redhat.com>
This commit is contained in:
Zhao Yakui 2010-01-06 22:05:57 +08:00 committed by Eric Anholt
parent ddc9003c35
commit a59e385eac
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/i915/intel_display.c
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@ -241,11 +241,11 @@ struct intel_limit {
#define IRONLAKE_VCO_MIN 1760000
#define IRONLAKE_VCO_MAX 3510000
#define IRONLAKE_N_MIN 1
#define IRONLAKE_N_MAX 5
#define IRONLAKE_N_MAX 6
#define IRONLAKE_M_MIN 79
#define IRONLAKE_M_MAX 118
#define IRONLAKE_M_MAX 127
#define IRONLAKE_M1_MIN 12
#define IRONLAKE_M1_MAX 23
#define IRONLAKE_M1_MAX 22
#define IRONLAKE_M2_MIN 5
#define IRONLAKE_M2_MAX 9
#define IRONLAKE_P_SDVO_DAC_MIN 5