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arm64: dts: r8a7795: Add cpuidle support for CA57 cores

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Enable cpuidle (core shutdown) support for R-Car H3 CA57 cores.

Parameters were found after evaluation by gaku.inami.xw@bp.renesas.com; they
help to keep the performance and reduce the power consumption.

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
[dien.pham.ry: Apply new cpuidle parameters]
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/1547808474-19427-2-git-send-email-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Khiem Nguyen
2019-01-18 11:47:50 +01:00
committed by Geert Uytterhoeven
parent 3c19b46a1f
commit a3ba116909
1 changed files with 17 additions and 0 deletions
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17
arch/arm64/boot/dts/renesas/r8a7795.dtsi
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@@ -155,6 +155,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>; power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <854>; dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
@@ -169,6 +170,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>; power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
@@ -182,6 +184,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>; power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
@@ -195,6 +198,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>; power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
@@ -264,6 +268,19 @@
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
}; };
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <500>;
min-residency-us = <4000>;
};
};
}; };
extal_clk: extal { extal_clk: extal {