Merge branch 'bcm_sf2-utilize-b53_common'
Florian Fainelli says:
====================
net: dsa: Make bcm_sf2 utilize b53_common
This patch series makes the bcm_sf2 driver utilize a large number of the core
functions offered by the b53_common driver since the SWITCH_CORE registers are
mostly register compatible with the switches driven by b53_common.
In order to accomplish that, we just override the dsa_driver_ops callbacks that
we need to. There are still integration specific logic from the bcm_sf2 that we
cannot absorb into b53_common because it is just not there, mostly in the area
of link management and power management, but most of the features are within
b53_common now: VLAN, FDB, bridge
Along the process, we also improve support for the BCM58xx SoCs, since those
also have the same version of the switching IP that 7445 has (for which bcm_sf2
was developed).
Changes in v3:
- rebase against 145dd5f9c8 ("net: flush the
softnet backlog in process context")
Changes in v2:
- rebased against "net: dsa: rename switch operations structure"
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
a29ca89460
@ -16,6 +16,7 @@ config NET_DSA_BCM_SF2
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select FIXED_PHY
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select BCM7XXX_PHY
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select MDIO_BCM_UNIMAC
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select B53
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---help---
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This enables support for the Broadcom Starfighter 2 Ethernet
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switch chips.
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@ -167,6 +167,65 @@ static const struct b53_mib_desc b53_mibs[] = {
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#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
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static const struct b53_mib_desc b53_mibs_58xx[] = {
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{ 8, 0x00, "TxOctets" },
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{ 4, 0x08, "TxDropPkts" },
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{ 4, 0x0c, "TxQPKTQ0" },
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{ 4, 0x10, "TxBroadcastPkts" },
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{ 4, 0x14, "TxMulticastPkts" },
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{ 4, 0x18, "TxUnicastPKts" },
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{ 4, 0x1c, "TxCollisions" },
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{ 4, 0x20, "TxSingleCollision" },
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{ 4, 0x24, "TxMultipleCollision" },
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{ 4, 0x28, "TxDeferredCollision" },
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{ 4, 0x2c, "TxLateCollision" },
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{ 4, 0x30, "TxExcessiveCollision" },
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{ 4, 0x34, "TxFrameInDisc" },
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{ 4, 0x38, "TxPausePkts" },
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{ 4, 0x3c, "TxQPKTQ1" },
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{ 4, 0x40, "TxQPKTQ2" },
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{ 4, 0x44, "TxQPKTQ3" },
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{ 4, 0x48, "TxQPKTQ4" },
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{ 4, 0x4c, "TxQPKTQ5" },
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{ 8, 0x50, "RxOctets" },
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{ 4, 0x58, "RxUndersizePkts" },
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{ 4, 0x5c, "RxPausePkts" },
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{ 4, 0x60, "RxPkts64Octets" },
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{ 4, 0x64, "RxPkts65to127Octets" },
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{ 4, 0x68, "RxPkts128to255Octets" },
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{ 4, 0x6c, "RxPkts256to511Octets" },
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{ 4, 0x70, "RxPkts512to1023Octets" },
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{ 4, 0x74, "RxPkts1024toMaxPktsOctets" },
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{ 4, 0x78, "RxOversizePkts" },
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{ 4, 0x7c, "RxJabbers" },
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{ 4, 0x80, "RxAlignmentErrors" },
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{ 4, 0x84, "RxFCSErrors" },
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{ 8, 0x88, "RxGoodOctets" },
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{ 4, 0x90, "RxDropPkts" },
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{ 4, 0x94, "RxUnicastPkts" },
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{ 4, 0x98, "RxMulticastPkts" },
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{ 4, 0x9c, "RxBroadcastPkts" },
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{ 4, 0xa0, "RxSAChanges" },
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{ 4, 0xa4, "RxFragments" },
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{ 4, 0xa8, "RxJumboPkt" },
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{ 4, 0xac, "RxSymblErr" },
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{ 4, 0xb0, "InRangeErrCount" },
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{ 4, 0xb4, "OutRangeErrCount" },
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{ 4, 0xb8, "EEELpiEvent" },
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{ 4, 0xbc, "EEELpiDuration" },
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{ 4, 0xc0, "RxDiscard" },
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{ 4, 0xc8, "TxQPKTQ6" },
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{ 4, 0xcc, "TxQPKTQ7" },
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{ 4, 0xd0, "TxPkts64Octets" },
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{ 4, 0xd4, "TxPkts65to127Octets" },
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{ 4, 0xd8, "TxPkts128to255Octets" },
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{ 4, 0xdc, "TxPkts256to511Ocets" },
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{ 4, 0xe0, "TxPkts512to1023Ocets" },
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{ 4, 0xe4, "TxPkts1024toMaxPktOcets" },
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};
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#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
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static int b53_do_vlan_op(struct b53_device *dev, u8 op)
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{
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unsigned int i;
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@ -635,6 +694,8 @@ static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
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return b53_mibs_65;
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else if (is63xx(dev))
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return b53_mibs_63xx;
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else if (is58xx(dev))
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return b53_mibs_58xx;
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else
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return b53_mibs;
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}
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@ -645,6 +706,8 @@ static unsigned int b53_get_mib_size(struct b53_device *dev)
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return B53_MIBS_65_SIZE;
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else if (is63xx(dev))
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return B53_MIBS_63XX_SIZE;
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else if (is58xx(dev))
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return B53_MIBS_58XX_SIZE;
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else
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return B53_MIBS_SIZE;
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}
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@ -1252,9 +1315,21 @@ static int b53_br_join(struct dsa_switch *ds, int port,
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struct net_device *bridge)
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{
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struct b53_device *dev = ds_to_priv(ds);
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s8 cpu_port = ds->dst->cpu_port;
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u16 pvlan, reg;
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unsigned int i;
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/* Make this port leave the all VLANs join since we will have proper
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* VLAN entries from now on
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*/
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if (is58xx(dev)) {
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b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
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reg &= ~BIT(port);
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if ((reg & BIT(cpu_port)) == BIT(cpu_port))
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reg &= ~BIT(cpu_port);
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b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
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}
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dev->ports[port].bridge_dev = bridge;
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b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
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@ -1287,6 +1362,7 @@ static void b53_br_leave(struct dsa_switch *ds, int port)
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struct b53_device *dev = ds_to_priv(ds);
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struct net_device *bridge = dev->ports[port].bridge_dev;
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struct b53_vlan *vl = &dev->vlans[0];
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s8 cpu_port = ds->dst->cpu_port;
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unsigned int i;
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u16 pvlan, reg, pvid;
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@ -1316,10 +1392,19 @@ static void b53_br_leave(struct dsa_switch *ds, int port)
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else
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pvid = 0;
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b53_get_vlan_entry(dev, pvid, vl);
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vl->members |= BIT(port) | BIT(dev->cpu_port);
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vl->untag |= BIT(port) | BIT(dev->cpu_port);
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b53_set_vlan_entry(dev, pvid, vl);
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/* Make this port join all VLANs without VLAN entries */
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if (is58xx(dev)) {
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b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
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reg |= BIT(port);
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if (!(reg & BIT(cpu_port)))
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reg |= BIT(cpu_port);
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b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
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} else {
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b53_get_vlan_entry(dev, pvid, vl);
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vl->members |= BIT(port) | BIT(dev->cpu_port);
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vl->untag |= BIT(port) | BIT(dev->cpu_port);
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b53_set_vlan_entry(dev, pvid, vl);
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}
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}
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static void b53_br_set_stp_state(struct dsa_switch *ds, int port,
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@ -1598,11 +1683,22 @@ static const struct b53_chip_data b53_switch_chips[] = {
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.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
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.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
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},
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{
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.chip_id = BCM7445_DEVICE_ID,
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.dev_name = "BCM7445",
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.vlans = 4096,
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.enabled_ports = 0x1ff,
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.arl_entries = 4,
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.cpu_port = B53_CPU_PORT,
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.vta_regs = B53_VTA_REGS,
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.duplex_reg = B53_DUPLEX_STAT_GE,
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.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
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.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
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},
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};
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static int b53_switch_init(struct b53_device *dev)
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{
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struct dsa_switch *ds = dev->ds;
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unsigned int i;
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int ret;
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@ -1618,7 +1714,6 @@ static int b53_switch_init(struct b53_device *dev)
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dev->vta_regs[1] = chip->vta_regs[1];
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dev->vta_regs[2] = chip->vta_regs[2];
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dev->jumbo_pm_reg = chip->jumbo_pm_reg;
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ds->ops = &b53_switch_ops;
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dev->cpu_port = chip->cpu_port;
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dev->num_vlans = chip->vlans;
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dev->num_arl_entries = chip->arl_entries;
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@ -1706,6 +1801,7 @@ struct b53_device *b53_switch_alloc(struct device *base,
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dev->ds = ds;
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dev->priv = priv;
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dev->ops = ops;
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ds->ops = &b53_switch_ops;
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mutex_init(&dev->reg_mutex);
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mutex_init(&dev->stats_mutex);
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@ -60,6 +60,7 @@ enum {
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BCM53018_DEVICE_ID = 0x53018,
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BCM53019_DEVICE_ID = 0x53019,
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BCM58XX_DEVICE_ID = 0x5800,
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BCM7445_DEVICE_ID = 0x7445,
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};
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#define B53_N_PORTS 9
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@ -174,6 +175,12 @@ static inline int is5301x(struct b53_device *dev)
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dev->chip_id == BCM53019_DEVICE_ID;
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}
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static inline int is58xx(struct b53_device *dev)
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{
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return dev->chip_id == BCM58XX_DEVICE_ID ||
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dev->chip_id == BCM7445_DEVICE_ID;
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}
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#define B53_CPU_PORT_25 5
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#define B53_CPU_PORT 8
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@ -309,6 +309,9 @@
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/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
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#define B53_PVLAN_PORT_MASK(i) ((i) * 2)
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/* Join all VLANs register (16 bit) */
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#define B53_JOIN_ALL_VLAN_EN 0x50
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/*************************************************************************
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* 802.1Q Page Registers
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*************************************************************************/
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File diff suppressed because it is too large
Load Diff
@ -26,6 +26,7 @@
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#include <net/dsa.h>
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#include "bcm_sf2_regs.h"
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#include "b53/b53_priv.h"
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struct bcm_sf2_hw_params {
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u16 top_rev;
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@ -50,71 +51,9 @@ struct bcm_sf2_port_status {
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struct ethtool_eee eee;
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u32 vlan_ctl_mask;
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u16 pvid;
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struct net_device *bridge_dev;
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u16 vlan_ctl_mask;
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};
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struct bcm_sf2_arl_entry {
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u8 port;
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u8 mac[ETH_ALEN];
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u16 vid;
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u8 is_valid:1;
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u8 is_age:1;
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u8 is_static:1;
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};
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struct bcm_sf2_vlan {
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u16 members;
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u16 untag;
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};
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static inline void bcm_sf2_mac_from_u64(u64 src, u8 *dst)
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{
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unsigned int i;
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for (i = 0; i < ETH_ALEN; i++)
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dst[ETH_ALEN - 1 - i] = (src >> (8 * i)) & 0xff;
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}
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static inline u64 bcm_sf2_mac_to_u64(const u8 *src)
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{
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unsigned int i;
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u64 dst = 0;
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for (i = 0; i < ETH_ALEN; i++)
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dst |= (u64)src[ETH_ALEN - 1 - i] << (8 * i);
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return dst;
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}
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static inline void bcm_sf2_arl_to_entry(struct bcm_sf2_arl_entry *ent,
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u64 mac_vid, u32 fwd_entry)
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{
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memset(ent, 0, sizeof(*ent));
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ent->port = fwd_entry & PORTID_MASK;
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ent->is_valid = !!(fwd_entry & ARL_VALID);
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ent->is_age = !!(fwd_entry & ARL_AGE);
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ent->is_static = !!(fwd_entry & ARL_STATIC);
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bcm_sf2_mac_from_u64(mac_vid, ent->mac);
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ent->vid = mac_vid >> VID_SHIFT;
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}
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static inline void bcm_sf2_arl_from_entry(u64 *mac_vid, u32 *fwd_entry,
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const struct bcm_sf2_arl_entry *ent)
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{
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*mac_vid = bcm_sf2_mac_to_u64(ent->mac);
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*mac_vid |= (u64)(ent->vid & VID_MASK) << VID_SHIFT;
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*fwd_entry = ent->port & PORTID_MASK;
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if (ent->is_valid)
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*fwd_entry |= ARL_VALID;
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if (ent->is_static)
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*fwd_entry |= ARL_STATIC;
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if (ent->is_age)
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*fwd_entry |= ARL_AGE;
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}
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struct bcm_sf2_priv {
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/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
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void __iomem *core;
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@ -134,6 +73,9 @@ struct bcm_sf2_priv {
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u32 irq1_stat;
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u32 irq1_mask;
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/* Backing b53_device */
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struct b53_device *dev;
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/* Mutex protecting access to the MIB counters */
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struct mutex stats_mutex;
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@ -155,16 +97,14 @@ struct bcm_sf2_priv {
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struct device_node *master_mii_dn;
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struct mii_bus *slave_mii_bus;
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struct mii_bus *master_mii_bus;
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/* Cache of programmed VLANs */
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struct bcm_sf2_vlan vlans[VLAN_N_VID];
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};
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struct bcm_sf2_hw_stats {
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const char *string;
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u16 reg;
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u8 sizeof_stat;
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};
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static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
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{
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struct b53_device *dev = ds_to_priv(ds);
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|
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return dev->priv;
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}
|
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#define SF2_IO_MACRO(name) \
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static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
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@ -115,14 +115,6 @@
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#define RX_BCST_EN (1 << 2)
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#define RX_MCST_EN (1 << 3)
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#define RX_UCST_EN (1 << 4)
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#define G_MISTP_STATE_SHIFT 5
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#define G_MISTP_NO_STP (0 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_DIS_STATE (1 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_BLOCK_STATE (2 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_LISTEN_STATE (3 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_LEARN_STATE (4 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_FWD_STATE (5 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_STATE_MASK 0x7
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#define CORE_SWMODE 0x0002c
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#define SW_FWDG_MODE (1 << 0)
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@ -205,75 +197,11 @@
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#define BRCM_HDR_EN_P5 (1 << 1)
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#define BRCM_HDR_EN_P7 (1 << 2)
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|
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#define CORE_BRCM_HDR_CTRL2 0x0828
|
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|
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#define CORE_HL_PRTC_CTRL 0x0940
|
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#define ARP_EN (1 << 0)
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#define RARP_EN (1 << 1)
|
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#define DHCP_EN (1 << 2)
|
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#define ICMPV4_EN (1 << 3)
|
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#define ICMPV6_EN (1 << 4)
|
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#define ICMPV6_FWD_MODE (1 << 5)
|
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#define IGMP_DIP_EN (1 << 8)
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#define IGMP_RPTLVE_EN (1 << 9)
|
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#define IGMP_RTPLVE_FWD_MODE (1 << 10)
|
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#define IGMP_QRY_EN (1 << 11)
|
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#define IGMP_QRY_FWD_MODE (1 << 12)
|
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#define IGMP_UKN_EN (1 << 13)
|
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#define IGMP_UKN_FWD_MODE (1 << 14)
|
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#define MLD_RPTDONE_EN (1 << 15)
|
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#define MLD_RPTDONE_FWD_MODE (1 << 16)
|
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#define MLD_QRY_EN (1 << 17)
|
||||
#define MLD_QRY_FWD_MODE (1 << 18)
|
||||
|
||||
#define CORE_RST_MIB_CNT_EN 0x0950
|
||||
|
||||
#define CORE_BRCM_HDR_RX_DIS 0x0980
|
||||
#define CORE_BRCM_HDR_TX_DIS 0x0988
|
||||
|
||||
#define CORE_ARLA_NUM_ENTRIES 1024
|
||||
|
||||
#define CORE_ARLA_RWCTL 0x1400
|
||||
#define ARL_RW (1 << 0)
|
||||
#define IVL_SVL_SELECT (1 << 6)
|
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#define ARL_STRTDN (1 << 7)
|
||||
|
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#define CORE_ARLA_MAC 0x1408
|
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#define CORE_ARLA_VID 0x1420
|
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#define ARLA_VIDTAB_INDX_MASK 0x1fff
|
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|
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#define CORE_ARLA_MACVID0 0x1440
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#define MAC_MASK 0xffffffffff
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#define VID_SHIFT 48
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#define VID_MASK 0xfff
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#define CORE_ARLA_FWD_ENTRY0 0x1460
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#define PORTID_MASK 0x1ff
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||||
#define ARL_CON_SHIFT 9
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#define ARL_CON_MASK 0x3
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#define ARL_PRI_SHIFT 11
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#define ARL_PRI_MASK 0x7
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#define ARL_AGE (1 << 14)
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#define ARL_STATIC (1 << 15)
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#define ARL_VALID (1 << 16)
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#define CORE_ARLA_MACVID_ENTRY(x) (CORE_ARLA_MACVID0 + ((x) * 0x40))
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||||
#define CORE_ARLA_FWD_ENTRY(x) (CORE_ARLA_FWD_ENTRY0 + ((x) * 0x40))
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||||
|
||||
#define CORE_ARLA_SRCH_CTL 0x1540
|
||||
#define ARLA_SRCH_VLID (1 << 0)
|
||||
#define IVL_SVL_SELECT (1 << 6)
|
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#define ARLA_SRCH_STDN (1 << 7)
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||||
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||||
#define CORE_ARLA_SRCH_ADR 0x1544
|
||||
#define ARLA_SRCH_ADR_VALID (1 << 15)
|
||||
|
||||
#define CORE_ARLA_SRCH_RSLT_0_MACVID 0x1580
|
||||
#define CORE_ARLA_SRCH_RSLT_0 0x15a0
|
||||
|
||||
#define CORE_ARLA_SRCH_RSLT_MACVID(x) (CORE_ARLA_SRCH_RSLT_0_MACVID + ((x) * 0x40))
|
||||
#define CORE_ARLA_SRCH_RSLT(x) (CORE_ARLA_SRCH_RSLT_0 + ((x) * 0x40))
|
||||
|
||||
#define CORE_ARLA_VTBL_RWCTRL 0x1600
|
||||
#define ARLA_VTBL_CMD_WRITE 0
|
||||
#define ARLA_VTBL_CMD_READ 1
|
||||
@ -297,59 +225,9 @@
|
||||
#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
|
||||
((x) * P_TXQ_PSM_VDD_SHIFT))
|
||||
|
||||
#define CORE_P0_MIB_OFFSET 0x8000
|
||||
#define P_MIB_SIZE 0x400
|
||||
#define CORE_P_MIB_OFFSET(x) (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
|
||||
|
||||
#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
|
||||
#define PORT_VLAN_CTRL_MASK 0x1ff
|
||||
|
||||
#define CORE_VLAN_CTRL0 0xd000
|
||||
#define CHANGE_1P_VID_INNER (1 << 0)
|
||||
#define CHANGE_1P_VID_OUTER (1 << 1)
|
||||
#define CHANGE_1Q_VID (1 << 3)
|
||||
#define VLAN_LEARN_MODE_SVL (0 << 5)
|
||||
#define VLAN_LEARN_MODE_IVL (3 << 5)
|
||||
#define VLAN_EN (1 << 7)
|
||||
|
||||
#define CORE_VLAN_CTRL1 0xd004
|
||||
#define EN_RSV_MCAST_FWDMAP (1 << 2)
|
||||
#define EN_RSV_MCAST_UNTAG (1 << 3)
|
||||
#define EN_IPMC_BYPASS_FWDMAP (1 << 5)
|
||||
#define EN_IPMC_BYPASS_UNTAG (1 << 6)
|
||||
|
||||
#define CORE_VLAN_CTRL2 0xd008
|
||||
#define EN_MIIM_BYPASS_V_FWDMAP (1 << 2)
|
||||
#define EN_GMRP_GVRP_V_FWDMAP (1 << 5)
|
||||
#define EN_GMRP_GVRP_UNTAG_MAP (1 << 6)
|
||||
|
||||
#define CORE_VLAN_CTRL3 0xd00c
|
||||
#define EN_DROP_NON1Q_MASK 0x1ff
|
||||
|
||||
#define CORE_VLAN_CTRL4 0xd014
|
||||
#define RESV_MCAST_FLOOD (1 << 1)
|
||||
#define EN_DOUBLE_TAG_MASK 0x3
|
||||
#define EN_DOUBLE_TAG_SHIFT 2
|
||||
#define EN_MGE_REV_GMRP (1 << 4)
|
||||
#define EN_MGE_REV_GVRP (1 << 5)
|
||||
#define INGR_VID_CHK_SHIFT 6
|
||||
#define INGR_VID_CHK_MASK 0x3
|
||||
#define INGR_VID_CHK_FWD (0 << INGR_VID_CHK_SHIFT)
|
||||
#define INGR_VID_CHK_DROP (1 << INGR_VID_CHK_SHIFT)
|
||||
#define INGR_VID_CHK_NO_CHK (2 << INGR_VID_CHK_SHIFT)
|
||||
#define INGR_VID_CHK_VID_VIOL_IMP (3 << INGR_VID_CHK_SHIFT)
|
||||
|
||||
#define CORE_VLAN_CTRL5 0xd018
|
||||
#define EN_CPU_RX_BYP_INNER_CRCCHCK (1 << 0)
|
||||
#define EN_VID_FFF_FWD (1 << 2)
|
||||
#define DROP_VTABLE_MISS (1 << 3)
|
||||
#define EGRESS_DIR_FRM_BYP_TRUNK_EN (1 << 4)
|
||||
#define PRESV_NON1Q (1 << 6)
|
||||
|
||||
#define CORE_VLAN_CTRL6 0xd01c
|
||||
#define STRICT_SFD_DETECT (1 << 0)
|
||||
#define DIS_ARL_BUST_LMIT (1 << 4)
|
||||
|
||||
#define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
|
||||
#define CFI_SHIFT 12
|
||||
#define PRI_SHIFT 13
|
||||
|
||||
Loading…
Reference in New Issue
Block a user