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gpio: ath79: make use of raw_spinlock variants

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The ath79 gpio driver currently implements an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel.  Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.

Signed-off-by: Julia Cartwright <julia@ni.com>
Acked-by: Aban Bedel <albeu@free.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Julia Cartwright 2017-03-09 10:21:53 -06:00 committed by Linus Walleij
parent c69fcea57e
commit a080ce53ee
1 changed files with 14 additions and 14 deletions
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28
drivers/gpio/gpio-ath79.c
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@ -32,7 +32,7 @@
struct ath79_gpio_ctrl { struct ath79_gpio_ctrl {
struct gpio_chip gc; struct gpio_chip gc;
void __iomem *base; void __iomem *base;
spinlock_t lock; raw_spinlock_t lock;
unsigned long both_edges; unsigned long both_edges;
}; };
@ -74,9 +74,9 @@ static void ath79_gpio_irq_unmask(struct irq_data *data)
u32 mask = BIT(irqd_to_hwirq(data)); u32 mask = BIT(irqd_to_hwirq(data));
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&ctrl->lock, flags); raw_spin_lock_irqsave(&ctrl->lock, flags);
ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
spin_unlock_irqrestore(&ctrl->lock, flags); raw_spin_unlock_irqrestore(&ctrl->lock, flags);
} }
static void ath79_gpio_irq_mask(struct irq_data *data) static void ath79_gpio_irq_mask(struct irq_data *data)
@ -85,9 +85,9 @@ static void ath79_gpio_irq_mask(struct irq_data *data)
u32 mask = BIT(irqd_to_hwirq(data)); u32 mask = BIT(irqd_to_hwirq(data));
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&ctrl->lock, flags); raw_spin_lock_irqsave(&ctrl->lock, flags);
ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
spin_unlock_irqrestore(&ctrl->lock, flags); raw_spin_unlock_irqrestore(&ctrl->lock, flags);
} }
static void ath79_gpio_irq_enable(struct irq_data *data) static void ath79_gpio_irq_enable(struct irq_data *data)
@ -96,10 +96,10 @@ static void ath79_gpio_irq_enable(struct irq_data *data)
u32 mask = BIT(irqd_to_hwirq(data)); u32 mask = BIT(irqd_to_hwirq(data));
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&ctrl->lock, flags); raw_spin_lock_irqsave(&ctrl->lock, flags);
ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
spin_unlock_irqrestore(&ctrl->lock, flags); raw_spin_unlock_irqrestore(&ctrl->lock, flags);
} }
static void ath79_gpio_irq_disable(struct irq_data *data) static void ath79_gpio_irq_disable(struct irq_data *data)
@ -108,10 +108,10 @@ static void ath79_gpio_irq_disable(struct irq_data *data)
u32 mask = BIT(irqd_to_hwirq(data)); u32 mask = BIT(irqd_to_hwirq(data));
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&ctrl->lock, flags); raw_spin_lock_irqsave(&ctrl->lock, flags);
ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
spin_unlock_irqrestore(&ctrl->lock, flags); raw_spin_unlock_irqrestore(&ctrl->lock, flags);
} }
static int ath79_gpio_irq_set_type(struct irq_data *data, static int ath79_gpio_irq_set_type(struct irq_data *data,
@ -140,7 +140,7 @@ static int ath79_gpio_irq_set_type(struct irq_data *data,
return -EINVAL; return -EINVAL;
} }
spin_lock_irqsave(&ctrl->lock, flags); raw_spin_lock_irqsave(&ctrl->lock, flags);
if (flow_type == IRQ_TYPE_EDGE_BOTH) { if (flow_type == IRQ_TYPE_EDGE_BOTH) {
ctrl->both_edges |= mask; ctrl->both_edges |= mask;
@ -165,7 +165,7 @@ static int ath79_gpio_irq_set_type(struct irq_data *data,
ath79_gpio_update_bits( ath79_gpio_update_bits(
ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
spin_unlock_irqrestore(&ctrl->lock, flags); raw_spin_unlock_irqrestore(&ctrl->lock, flags);
return 0; return 0;
} }
@ -191,7 +191,7 @@ static void ath79_gpio_irq_handler(struct irq_desc *desc)
chained_irq_enter(irqchip, desc); chained_irq_enter(irqchip, desc);
spin_lock_irqsave(&ctrl->lock, flags); raw_spin_lock_irqsave(&ctrl->lock, flags);
pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
@ -203,7 +203,7 @@ static void ath79_gpio_irq_handler(struct irq_desc *desc)
both_edges, ~state); both_edges, ~state);
} }
spin_unlock_irqrestore(&ctrl->lock, flags); raw_spin_unlock_irqrestore(&ctrl->lock, flags);
if (pending) { if (pending) {
for_each_set_bit(irq, &pending, gc->ngpio) for_each_set_bit(irq, &pending, gc->ngpio)
@ -262,7 +262,7 @@ static int ath79_gpio_probe(struct platform_device *pdev)
if (!ctrl->base) if (!ctrl->base)
return -ENOMEM; return -ENOMEM;
spin_lock_init(&ctrl->lock); raw_spin_lock_init(&ctrl->lock);
err = bgpio_init(&ctrl->gc, &pdev->dev, 4, err = bgpio_init(&ctrl->gc, &pdev->dev, 4,
ctrl->base + AR71XX_GPIO_REG_IN, ctrl->base + AR71XX_GPIO_REG_IN,
ctrl->base + AR71XX_GPIO_REG_SET, ctrl->base + AR71XX_GPIO_REG_SET,