forked from Minki/linux
powerpc/selftests: Check endianness on trap in TM
Add a selftest to check if endianness is flipped inadvertently to BE (MSR.LE set to zero) on BE and LE machines when a trap is caught in transactional mode and load_fp and load_vec are zero, i.e. when MSR.FP and MSR.VEC are zeroed (disabled). Signed-off-by: Gustavo Romero <gromero@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Gustavo Romero
Michael Ellerman
parent
1c200e63d0
commit
a08082f8e4
@ -13,3 +13,4 @@ tm-signal-context-chk-vmx
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tm-signal-context-chk-vsx
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tm-vmx-unavail
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tm-unavailable
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tm-trap
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@ -3,7 +3,7 @@ SIGNAL_CONTEXT_CHK_TESTS := tm-signal-context-chk-gpr tm-signal-context-chk-fpu
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tm-signal-context-chk-vmx tm-signal-context-chk-vsx
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TEST_GEN_PROGS := tm-resched-dscr tm-syscall tm-signal-msr-resv tm-signal-stack \
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tm-vmxcopy tm-fork tm-tar tm-tmspr tm-vmx-unavail tm-unavailable \
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tm-vmxcopy tm-fork tm-tar tm-tmspr tm-vmx-unavail tm-unavailable tm-trap \
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$(SIGNAL_CONTEXT_CHK_TESTS)
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include ../../lib.mk
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@ -18,6 +18,7 @@ $(OUTPUT)/tm-tmspr: CFLAGS += -pthread
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$(OUTPUT)/tm-vmx-unavail: CFLAGS += -pthread -m64
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$(OUTPUT)/tm-resched-dscr: ../pmu/lib.o
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$(OUTPUT)/tm-unavailable: CFLAGS += -O0 -pthread -m64 -Wno-error=uninitialized -mvsx
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$(OUTPUT)/tm-trap: CFLAGS += -O0 -pthread -m64
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SIGNAL_CONTEXT_CHK_TESTS := $(patsubst %,$(OUTPUT)/%,$(SIGNAL_CONTEXT_CHK_TESTS))
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$(SIGNAL_CONTEXT_CHK_TESTS): tm-signal.S
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329
tools/testing/selftests/powerpc/tm/tm-trap.c
Normal file
329
tools/testing/selftests/powerpc/tm/tm-trap.c
Normal file
@ -0,0 +1,329 @@
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/*
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* Copyright 2017, Gustavo Romero, IBM Corp.
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* Licensed under GPLv2.
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*
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* Check if thread endianness is flipped inadvertently to BE on trap
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* caught in TM whilst MSR.FP and MSR.VEC are zero (i.e. just after
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* load_fp and load_vec overflowed).
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*
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* The issue can be checked on LE machines simply by zeroing load_fp
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* and load_vec and then causing a trap in TM. Since the endianness
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* changes to BE on return from the signal handler, 'nop' is
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* thread as an illegal instruction in following sequence:
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* tbegin.
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* beq 1f
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* trap
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* tend.
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* 1: nop
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*
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* However, although the issue is also present on BE machines, it's a
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* bit trickier to check it on BE machines because MSR.LE bit is set
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* to zero which determines a BE endianness that is the native
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* endianness on BE machines, so nothing notably critical happens,
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* i.e. no illegal instruction is observed immediately after returning
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* from the signal handler (as it happens on LE machines). Thus to test
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* it on BE machines LE endianness is forced after a first trap and then
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* the endianness is verified on subsequent traps to determine if the
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* endianness "flipped back" to the native endianness (BE).
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*/
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#define _GNU_SOURCE
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#include <error.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <htmintrin.h>
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#include <inttypes.h>
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#include <pthread.h>
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#include <sched.h>
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#include <signal.h>
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#include <stdbool.h>
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#include "tm.h"
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#include "utils.h"
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#define pr_error(error_code, format, ...) \
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error_at_line(1, error_code, __FILE__, __LINE__, format, ##__VA_ARGS__)
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#define MSR_LE 1UL
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#define LE 1UL
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pthread_t t0_ping;
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pthread_t t1_pong;
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int exit_from_pong;
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int trap_event;
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int le;
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bool success;
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void trap_signal_handler(int signo, siginfo_t *si, void *uc)
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{
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ucontext_t *ucp = uc;
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uint64_t thread_endianness;
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/* Get thread endianness: extract bit LE from MSR */
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thread_endianness = MSR_LE & ucp->uc_mcontext.gp_regs[PT_MSR];
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/***
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* Little-Endian Machine
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*/
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if (le) {
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/* First trap event */
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if (trap_event == 0) {
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/* Do nothing. Since it is returning from this trap
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* event that endianness is flipped by the bug, so just
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* let the process return from the signal handler and
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* check on the second trap event if endianness is
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* flipped or not.
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*/
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}
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/* Second trap event */
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else if (trap_event == 1) {
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/*
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* Since trap was caught in TM on first trap event, if
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* endianness was still LE (not flipped inadvertently)
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* after returning from the signal handler instruction
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* (1) is executed (basically a 'nop'), as it's located
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* at address of tbegin. +4 (rollback addr). As (1) on
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* LE endianness does in effect nothing, instruction (2)
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* is then executed again as 'trap', generating a second
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* trap event (note that in that case 'trap' is caught
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* not in transacional mode). On te other hand, if after
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* the return from the signal handler the endianness in-
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* advertently flipped, instruction (1) is tread as a
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* branch instruction, i.e. b .+8, hence instruction (3)
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* and (4) are executed (tbegin.; trap;) and we get sim-
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* ilaly on the trap signal handler, but now in TM mode.
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* Either way, it's now possible to check the MSR LE bit
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* once in the trap handler to verify if endianness was
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* flipped or not after the return from the second trap
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* event. If endianness is flipped, the bug is present.
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* Finally, getting a trap in TM mode or not is just
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* worth noting because it affects the math to determine
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* the offset added to the NIP on return: the NIP for a
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* trap caught in TM is the rollback address, i.e. the
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* next instruction after 'tbegin.', whilst the NIP for
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* a trap caught in non-transactional mode is the very
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* same address of the 'trap' instruction that generated
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* the trap event.
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*/
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if (thread_endianness == LE) {
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/* Go to 'success', i.e. instruction (6) */
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ucp->uc_mcontext.gp_regs[PT_NIP] += 16;
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} else {
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/*
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* Thread endianness is BE, so it flipped
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* inadvertently. Thus we flip back to LE and
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* set NIP to go to 'failure', instruction (5).
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*/
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ucp->uc_mcontext.gp_regs[PT_MSR] |= 1UL;
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ucp->uc_mcontext.gp_regs[PT_NIP] += 4;
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}
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}
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}
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/***
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* Big-Endian Machine
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*/
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else {
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/* First trap event */
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if (trap_event == 0) {
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/*
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* Force thread endianness to be LE. Instructions (1),
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* (3), and (4) will be executed, generating a second
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* trap in TM mode.
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*/
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ucp->uc_mcontext.gp_regs[PT_MSR] |= 1UL;
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}
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/* Second trap event */
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else if (trap_event == 1) {
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/*
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* Do nothing. If bug is present on return from this
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* second trap event endianness will flip back "automat-
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* ically" to BE, otherwise thread endianness will
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* continue to be LE, just as it was set above.
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*/
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}
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/* A third trap event */
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else {
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/*
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* Once here it means that after returning from the sec-
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* ond trap event instruction (4) (trap) was executed
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* as LE, generating a third trap event. In that case
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* endianness is still LE as set on return from the
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* first trap event, hence no bug. Otherwise, bug
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* flipped back to BE on return from the second trap
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* event and instruction (4) was executed as 'tdi' (so
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* basically a 'nop') and branch to 'failure' in
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* instruction (5) was taken to indicate failure and we
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* never get here.
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*/
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/*
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* Flip back to BE and go to instruction (6), i.e. go to
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* 'success'.
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*/
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ucp->uc_mcontext.gp_regs[PT_MSR] &= ~1UL;
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ucp->uc_mcontext.gp_regs[PT_NIP] += 8;
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}
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}
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trap_event++;
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}
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void usr1_signal_handler(int signo, siginfo_t *si, void *not_used)
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{
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/* Got a USR1 signal from ping(), so just tell pong() to exit */
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exit_from_pong = 1;
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}
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void *ping(void *not_used)
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{
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uint64_t i;
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trap_event = 0;
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/*
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* Wait an amount of context switches so load_fp and load_vec overflows
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* and MSR_[FP|VEC|V] is 0.
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*/
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for (i = 0; i < 1024*1024*512; i++)
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;
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asm goto(
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/*
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* [NA] means "Native Endianness", i.e. it tells how a
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* instruction is executed on machine's native endianness (in
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* other words, native endianness matches kernel endianness).
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* [OP] means "Opposite Endianness", i.e. on a BE machine, it
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* tells how a instruction is executed as a LE instruction; con-
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* versely, on a LE machine, it tells how a instruction is
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* executed as a BE instruction. When [NA] is omitted, it means
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* that the native interpretation of a given instruction is not
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* relevant for the test. Likewise when [OP] is omitted.
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*/
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" tbegin. ;" /* (0) tbegin. [NA] */
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" tdi 0, 0, 0x48;" /* (1) nop [NA]; b (3) [OP] */
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" trap ;" /* (2) trap [NA] */
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".long 0x1D05007C;" /* (3) tbegin. [OP] */
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".long 0x0800E07F;" /* (4) trap [OP]; nop [NA] */
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" b %l[failure] ;" /* (5) b [NA]; MSR.LE flipped (bug) */
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" b %l[success] ;" /* (6) b [NA]; MSR.LE did not flip (ok)*/
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: : : : failure, success);
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failure:
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success = false;
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goto exit_from_ping;
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success:
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success = true;
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exit_from_ping:
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/* Tell pong() to exit before leaving */
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pthread_kill(t1_pong, SIGUSR1);
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return NULL;
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}
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void *pong(void *not_used)
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{
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while (!exit_from_pong)
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/*
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* Induce context switches on ping() thread
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* until ping() finishes its job and signs
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* to exit from this loop.
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*/
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sched_yield();
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return NULL;
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}
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int tm_trap_test(void)
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{
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uint16_t k = 1;
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int rc;
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pthread_attr_t attr;
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cpu_set_t cpuset;
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struct sigaction trap_sa;
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trap_sa.sa_flags = SA_SIGINFO;
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trap_sa.sa_sigaction = trap_signal_handler;
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sigaction(SIGTRAP, &trap_sa, NULL);
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struct sigaction usr1_sa;
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usr1_sa.sa_flags = SA_SIGINFO;
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usr1_sa.sa_sigaction = usr1_signal_handler;
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sigaction(SIGUSR1, &usr1_sa, NULL);
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/* Set only CPU 0 in the mask. Both threads will be bound to cpu 0. */
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CPU_ZERO(&cpuset);
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CPU_SET(0, &cpuset);
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/* Init pthread attribute */
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rc = pthread_attr_init(&attr);
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if (rc)
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pr_error(rc, "pthread_attr_init()");
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/*
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* Bind thread ping() and pong() both to CPU 0 so they ping-pong and
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* speed up context switches on ping() thread, speeding up the load_fp
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* and load_vec overflow.
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*/
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rc = pthread_attr_setaffinity_np(&attr, sizeof(cpu_set_t), &cpuset);
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if (rc)
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pr_error(rc, "pthread_attr_setaffinity()");
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/* Figure out the machine endianness */
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le = (int) *(uint8_t *)&k;
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printf("%s machine detected. Checking if endianness flips %s",
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le ? "Little-Endian" : "Big-Endian",
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"inadvertently on trap in TM... ");
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rc = fflush(0);
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if (rc)
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pr_error(rc, "fflush()");
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/* Launch ping() */
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rc = pthread_create(&t0_ping, &attr, ping, NULL);
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if (rc)
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pr_error(rc, "pthread_create()");
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exit_from_pong = 0;
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/* Launch pong() */
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rc = pthread_create(&t1_pong, &attr, pong, NULL);
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if (rc)
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pr_error(rc, "pthread_create()");
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rc = pthread_join(t0_ping, NULL);
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if (rc)
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pr_error(rc, "pthread_join()");
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rc = pthread_join(t1_pong, NULL);
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if (rc)
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pr_error(rc, "pthread_join()");
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if (success) {
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printf("no.\n"); /* no, endianness did not flip inadvertently */
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return EXIT_SUCCESS;
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}
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printf("yes!\n"); /* yes, endianness did flip inadvertently */
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return EXIT_FAILURE;
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}
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int main(int argc, char **argv)
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{
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return test_harness(tm_trap_test, "tm_trap_test");
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}
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