forked from Minki/linux
sky2: pci power savings
Turn on special bits to save more power when device is shutdown. Tested on a limited range of hardware, some of the bits are for hardware that probably isn't even in production (like Yukon Supreme) and was ported from the vendor driver. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
db99b98885
commit
a068c0adf2
@ -284,6 +284,86 @@ static void sky2_power_aux(struct sky2_hw *hw)
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PC_VAUX_ON | PC_VCC_OFF));
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}
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static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
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{
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u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
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int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
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u32 reg;
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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switch (state) {
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case PCI_D0:
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break;
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case PCI_D1:
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power_control |= 1;
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break;
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case PCI_D2:
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power_control |= 2;
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break;
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case PCI_D3hot:
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case PCI_D3cold:
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power_control |= 3;
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if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
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/* additional power saving measurements */
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reg = sky2_pci_read32(hw, PCI_DEV_REG4);
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/* set gating core clock for LTSSM in L1 state */
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reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
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/* auto clock gated scheme controlled by CLKREQ */
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P_ASPM_A1_MODE_SELECT |
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/* enable Gate Root Core Clock */
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P_CLK_GATE_ROOT_COR_ENA;
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if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
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/* enable Clock Power Management (CLKREQ) */
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u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
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ctrl |= PCI_EXP_DEVCTL_AUX_PME;
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sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
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} else
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/* force CLKREQ Enable in Our4 (A1b only) */
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reg |= P_ASPM_FORCE_CLKREQ_ENA;
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/* set Mask Register for Release/Gate Clock */
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sky2_pci_write32(hw, PCI_DEV_REG5,
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P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
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P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
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P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
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} else
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sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
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/* put CPU into reset state */
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sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
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if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
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/* put CPU into halt state */
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sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
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if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
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reg = sky2_pci_read32(hw, PCI_DEV_REG1);
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/* force to PCIe L1 */
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reg |= PCI_FORCE_PEX_L1;
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sky2_pci_write32(hw, PCI_DEV_REG1, reg);
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}
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break;
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default:
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dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
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state);
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return;
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}
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power_control |= PCI_PM_CTRL_PME_ENABLE;
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/* Finally, set the new power state. */
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sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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sky2_pci_read32(hw, B0_CTST);
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}
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static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
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{
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u16 reg;
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@ -2786,6 +2866,10 @@ static int __devinit sky2_init(struct sky2_hw *hw)
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hw->flags = SKY2_HW_GIGABIT
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| SKY2_HW_NEWER_PHY
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| SKY2_HW_ADV_POWER_CTL;
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/* check for Rev. A1 dev 4200 */
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if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
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hw->flags |= SKY2_HW_CLK_POWER;
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break;
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case CHIP_ID_YUKON_EX:
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@ -2836,6 +2920,11 @@ static int __devinit sky2_init(struct sky2_hw *hw)
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if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
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hw->flags |= SKY2_HW_FIBRE_PHY;
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hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
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if (hw->pm_cap == 0) {
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dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
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return -EIO;
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}
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hw->ports = 1;
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t8 = sky2_read8(hw, B2_Y2_HW_RES);
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@ -4407,7 +4496,7 @@ static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
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pci_save_state(pdev);
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pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
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pci_set_power_state(pdev, pci_choose_state(pdev, state));
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sky2_power_state(hw, pci_choose_state(pdev, state));
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return 0;
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}
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@ -4420,9 +4509,7 @@ static int sky2_resume(struct pci_dev *pdev)
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if (!hw)
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return 0;
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err = pci_set_power_state(pdev, PCI_D0);
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if (err)
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goto out;
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sky2_power_state(hw, PCI_D0);
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err = pci_restore_state(pdev);
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if (err)
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@ -4490,8 +4577,7 @@ static void sky2_shutdown(struct pci_dev *pdev)
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pci_enable_wake(pdev, PCI_D3cold, wol);
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D3hot);
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sky2_power_state(hw, PCI_D3hot);
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}
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static struct pci_driver sky2_driver = {
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@ -28,6 +28,11 @@ enum pci_dev_reg_1 {
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PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
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PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
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PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
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PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
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PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
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PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
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};
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enum pci_dev_reg_2 {
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@ -45,7 +50,11 @@ enum pci_dev_reg_2 {
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/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
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enum pci_dev_reg_4 {
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/* (Link Training & Status State Machine) */
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/* (Link Training & Status State Machine) */
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P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
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#define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK)
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P_PEX_LTSSM_L1_STAT = 0x34,
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P_PEX_LTSSM_DET_STAT = 0x01,
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P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
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/* (Active State Power Management) */
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P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
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@ -454,6 +463,9 @@ enum yukon_ex_rev {
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CHIP_REV_YU_EX_A0 = 1,
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CHIP_REV_YU_EX_B0 = 2,
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};
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enum yukon_supr_rev {
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CHIP_REV_YU_SU_A0 = 0,
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};
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/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
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@ -2059,7 +2071,9 @@ struct sky2_hw {
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#define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
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#define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
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#define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
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#define SKY2_HW_CLK_POWER 0x00000100 /* clock power management */
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int pm_cap;
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u8 chip_id;
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u8 chip_rev;
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u8 pmd_type;
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