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drm/i915: Precompute/readout/check CHV CGM mode

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Let's precompute the CGM mode for CHV. And naturally we
also read it out and check it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190218193137.22914-3-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
This commit is contained in:
Ville Syrjälä 2019-02-18 21:31:32 +02:00
parent a1f1e61bfb
commit 9fdfb8e730
3 changed files with 35 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
drivers/gpu/drm/i915/intel_color.c
View File

@ -294,7 +294,6 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 mode;
if (crtc_state->base.ctm) {
const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
@ -328,12 +327,7 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
}
mode = (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
if (!crtc_state_is_legacy_gamma(crtc_state)) {
mode |= (crtc_state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
(crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
}
I915_WRITE(CGM_PIPE_MODE(pipe), mode);
I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
}
/* Loads the legacy palette/gamma unit for the CRTC. */
@ -753,6 +747,23 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
return 0;
}
static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
{
u32 cgm_mode = 0;
if (crtc_state_is_legacy_gamma(crtc_state))
return 0;
if (crtc_state->base.degamma_lut)
cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
if (crtc_state->base.ctm)
cgm_mode |= CGM_PIPE_MODE_CSC;
if (crtc_state->base.gamma_lut)
cgm_mode |= CGM_PIPE_MODE_GAMMA;
return cgm_mode;
}
int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
@ -790,6 +801,9 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
crtc_state->csc_mode = 0;
if (IS_CHERRYVIEW(dev_priv))
crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
/* Always allow legacy gamma LUT with no further checking. */
if (!crtc_state->gamma_enable ||
crtc_state_is_legacy_gamma(crtc_state)) {

8
drivers/gpu/drm/i915/intel_display.c
View File

@ -8216,6 +8216,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
PIPECONF_GAMMA_MODE_SHIFT;
if (IS_CHERRYVIEW(dev_priv))
pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
i9xx_get_pipe_color_config(pipe_config);
if (INTEL_GEN(dev_priv) < 4)
@ -12238,7 +12241,10 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
PIPE_CONF_CHECK_X(gamma_mode);
PIPE_CONF_CHECK_X(csc_mode);
if (IS_CHERRYVIEW(dev_priv))
PIPE_CONF_CHECK_X(cgm_mode);
else
PIPE_CONF_CHECK_X(csc_mode);
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
}

9
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1021,8 +1021,13 @@ struct intel_crtc_state {
/* Gamma mode programmed on the pipe */
u32 gamma_mode;
/* CSC mode programmed on the pipe */
u32 csc_mode;
union {
/* CSC mode programmed on the pipe */
u32 csc_mode;
/* CHV CGM mode */
u32 cgm_mode;
};
/* bitmask of visible planes (enum plane_id) */
u8 active_planes;