forked from Minki/linux
Char/Misc fixes for 6.1-rc3
Here are some small driver fixes for 6.1-rc3. They include: - iio driver bugfixes - counter driver bugfixes - coresight bugfixes, including a revert and then a second fix to get it right. All of these have been in linux-next with no reported problems. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCY16EAA8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+yloyQCdFV2qLAb6IK+fx9rS8ThuxT13O5AAn1ec8Fd6 BSWYN1TIO6r83khtJ8y4 =34Sj -----END PGP SIGNATURE----- Merge tag 'char-misc-6.1-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc fixes from Greg KH: "Some small driver fixes for 6.1-rc3. They include: - iio driver bugfixes - counter driver bugfixes - coresight bugfixes, including a revert and then a second fix to get it right. All of these have been in linux-next with no reported problems" * tag 'char-misc-6.1-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (21 commits) misc: sgi-gru: use explicitly signed char coresight: cti: Fix hang in cti_disable_hw() Revert "coresight: cti: Fix hang in cti_disable_hw()" counter: 104-quad-8: Fix race getting function mode and direction counter: microchip-tcb-capture: Handle Signal1 read and Synapse coresight: cti: Fix hang in cti_disable_hw() coresight: Fix possible deadlock with lock dependency counter: ti-ecap-capture: fix IS_ERR() vs NULL check counter: Reduce DEFINE_COUNTER_ARRAY_POLARITY() to defining counter_array iio: bmc150-accel-core: Fix unsafe buffer attributes iio: adxl367: Fix unsafe buffer attributes iio: adxl372: Fix unsafe buffer attributes iio: at91-sama5d2_adc: Fix unsafe buffer attributes iio: temperature: ltc2983: allocate iio channels once tools: iio: iio_utils: fix digit calculation iio: adc: stm32-adc: fix channel sampling time init iio: adc: mcp3911: mask out device ID in debug prints iio: adc: mcp3911: use correct id bits iio: adc: mcp3911: return proper error code on failure to allocate trigger iio: adc: mcp3911: fix sizeof() vs ARRAY_SIZE() bug ...
This commit is contained in:
commit
9f127546bb
@ -232,34 +232,45 @@ static const enum counter_function quad8_count_functions_list[] = {
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COUNTER_FUNCTION_QUADRATURE_X4,
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};
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static int quad8_function_get(const struct quad8 *const priv, const size_t id,
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enum counter_function *const function)
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{
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if (!priv->quadrature_mode[id]) {
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*function = COUNTER_FUNCTION_PULSE_DIRECTION;
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return 0;
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}
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switch (priv->quadrature_scale[id]) {
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case 0:
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*function = COUNTER_FUNCTION_QUADRATURE_X1_A;
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return 0;
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case 1:
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*function = COUNTER_FUNCTION_QUADRATURE_X2_A;
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return 0;
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case 2:
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*function = COUNTER_FUNCTION_QUADRATURE_X4;
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return 0;
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default:
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/* should never reach this path */
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return -EINVAL;
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}
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}
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static int quad8_function_read(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function *function)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int id = count->id;
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unsigned long irqflags;
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int retval;
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spin_lock_irqsave(&priv->lock, irqflags);
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if (priv->quadrature_mode[id])
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switch (priv->quadrature_scale[id]) {
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case 0:
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*function = COUNTER_FUNCTION_QUADRATURE_X1_A;
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break;
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case 1:
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*function = COUNTER_FUNCTION_QUADRATURE_X2_A;
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break;
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case 2:
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*function = COUNTER_FUNCTION_QUADRATURE_X4;
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break;
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}
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else
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*function = COUNTER_FUNCTION_PULSE_DIRECTION;
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retval = quad8_function_get(priv, count->id, function);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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return retval;
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}
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static int quad8_function_write(struct counter_device *counter,
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@ -359,6 +370,7 @@ static int quad8_action_read(struct counter_device *counter,
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enum counter_synapse_action *action)
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{
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struct quad8 *const priv = counter_priv(counter);
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unsigned long irqflags;
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int err;
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enum counter_function function;
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const size_t signal_a_id = count->synapses[0].signal->id;
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@ -374,9 +386,21 @@ static int quad8_action_read(struct counter_device *counter,
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return 0;
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}
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err = quad8_function_read(counter, count, &function);
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if (err)
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Get Count function and direction atomically */
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err = quad8_function_get(priv, count->id, &function);
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if (err) {
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return err;
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}
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err = quad8_direction_read(counter, count, &direction);
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if (err) {
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return err;
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}
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spin_unlock_irqrestore(&priv->lock, irqflags);
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/* Default action mode */
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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@ -389,10 +413,6 @@ static int quad8_action_read(struct counter_device *counter,
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X1_A:
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if (synapse->signal->id == signal_a_id) {
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err = quad8_direction_read(counter, count, &direction);
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if (err)
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return err;
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if (direction == COUNTER_COUNT_DIRECTION_FORWARD)
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*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
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else
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@ -28,7 +28,6 @@ struct mchp_tc_data {
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int qdec_mode;
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int num_channels;
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int channel[2];
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bool trig_inverted;
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};
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static const enum counter_function mchp_tc_count_functions[] = {
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@ -153,7 +152,7 @@ static int mchp_tc_count_signal_read(struct counter_device *counter,
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regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
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if (priv->trig_inverted)
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if (signal->id == 1)
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sigstatus = (sr & ATMEL_TC_MTIOB);
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else
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sigstatus = (sr & ATMEL_TC_MTIOA);
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@ -171,6 +170,17 @@ static int mchp_tc_count_action_read(struct counter_device *counter,
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struct mchp_tc_data *const priv = counter_priv(counter);
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u32 cmr;
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if (priv->qdec_mode) {
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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return 0;
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}
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/* Only TIOA signal is evaluated in non-QDEC mode */
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if (synapse->signal->id != 0) {
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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return 0;
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}
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regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
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switch (cmr & ATMEL_TC_ETRGEDG) {
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@ -199,8 +209,8 @@ static int mchp_tc_count_action_write(struct counter_device *counter,
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struct mchp_tc_data *const priv = counter_priv(counter);
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u32 edge = ATMEL_TC_ETRGEDG_NONE;
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/* QDEC mode is rising edge only */
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if (priv->qdec_mode)
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/* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */
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if (priv->qdec_mode || synapse->signal->id != 0)
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return -EINVAL;
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switch (action) {
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@ -377,7 +377,8 @@ static const enum counter_signal_polarity ecap_cnt_pol_avail[] = {
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COUNTER_SIGNAL_POLARITY_NEGATIVE,
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};
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static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_avail, ECAP_NB_CEVT);
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static DEFINE_COUNTER_AVAILABLE(ecap_cnt_pol_available, ecap_cnt_pol_avail);
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static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_available, ECAP_NB_CEVT);
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static struct counter_comp ecap_cnt_signal_ext[] = {
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COUNTER_COMP_ARRAY_POLARITY(ecap_cnt_pol_read, ecap_cnt_pol_write, ecap_cnt_pol_array),
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@ -479,8 +480,8 @@ static int ecap_cnt_probe(struct platform_device *pdev)
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int ret;
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counter_dev = devm_counter_alloc(dev, sizeof(*ecap_dev));
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if (IS_ERR(counter_dev))
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return PTR_ERR(counter_dev);
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if (!counter_dev)
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return -ENOMEM;
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counter_dev->name = ECAP_DRV_NAME;
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counter_dev->parent = dev;
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@ -1687,14 +1687,15 @@ struct coresight_device *coresight_register(struct coresight_desc *desc)
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ret = coresight_fixup_device_conns(csdev);
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if (!ret)
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ret = coresight_fixup_orphan_conns(csdev);
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if (!ret && cti_assoc_ops && cti_assoc_ops->add)
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cti_assoc_ops->add(csdev);
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out_unlock:
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mutex_unlock(&coresight_mutex);
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/* Success */
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if (!ret)
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if (!ret) {
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if (cti_assoc_ops && cti_assoc_ops->add)
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cti_assoc_ops->add(csdev);
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return csdev;
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}
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/* Unregister the device if needed */
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if (registered) {
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@ -90,11 +90,9 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
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static int cti_enable_hw(struct cti_drvdata *drvdata)
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{
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struct cti_config *config = &drvdata->config;
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struct device *dev = &drvdata->csdev->dev;
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unsigned long flags;
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int rc = 0;
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pm_runtime_get_sync(dev->parent);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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/* no need to do anything if enabled or unpowered*/
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@ -119,7 +117,6 @@ cti_state_unchanged:
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/* cannot enable due to error */
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cti_err_not_enabled:
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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pm_runtime_put(dev->parent);
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return rc;
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}
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@ -153,7 +150,6 @@ cti_hp_not_enabled:
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static int cti_disable_hw(struct cti_drvdata *drvdata)
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{
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struct cti_config *config = &drvdata->config;
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struct device *dev = &drvdata->csdev->dev;
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struct coresight_device *csdev = drvdata->csdev;
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spin_lock(&drvdata->spinlock);
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@ -175,7 +171,6 @@ static int cti_disable_hw(struct cti_drvdata *drvdata)
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coresight_disclaim_device_unlocked(csdev);
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CS_LOCK(drvdata->base);
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spin_unlock(&drvdata->spinlock);
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pm_runtime_put(dev->parent);
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return 0;
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/* not disabled this call */
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@ -541,7 +536,7 @@ cti_match_fixup_csdev(struct cti_device *ctidev, const char *node_name,
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/*
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* Search the cti list to add an associated CTI into the supplied CS device
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* This will set the association if CTI declared before the CS device.
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* (called from coresight_register() with coresight_mutex locked).
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* (called from coresight_register() without coresight_mutex locked).
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*/
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static void cti_add_assoc_to_csdev(struct coresight_device *csdev)
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{
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@ -569,7 +564,8 @@ static void cti_add_assoc_to_csdev(struct coresight_device *csdev)
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* if we found a matching csdev then update the ECT
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* association pointer for the device with this CTI.
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*/
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csdev->ect_dev = ect_item->csdev;
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coresight_set_assoc_ectdev_mutex(csdev->ect_dev,
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ect_item->csdev);
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break;
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}
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}
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@ -1185,17 +1185,30 @@ static ssize_t adxl367_get_fifo_watermark(struct device *dev,
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return sysfs_emit(buf, "%d\n", fifo_watermark);
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}
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static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
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static IIO_CONST_ATTR(hwfifo_watermark_max,
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__stringify(ADXL367_FIFO_MAX_WATERMARK));
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static ssize_t hwfifo_watermark_min_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sysfs_emit(buf, "%s\n", "1");
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}
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static ssize_t hwfifo_watermark_max_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sysfs_emit(buf, "%s\n", __stringify(ADXL367_FIFO_MAX_WATERMARK));
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}
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static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
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static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
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static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
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adxl367_get_fifo_watermark, NULL, 0);
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static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
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adxl367_get_fifo_enabled, NULL, 0);
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static const struct attribute *adxl367_fifo_attributes[] = {
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&iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
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&iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
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&iio_dev_attr_hwfifo_watermark_min.dev_attr.attr,
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&iio_dev_attr_hwfifo_watermark_max.dev_attr.attr,
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&iio_dev_attr_hwfifo_watermark.dev_attr.attr,
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&iio_dev_attr_hwfifo_enabled.dev_attr.attr,
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NULL,
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|
@ -998,17 +998,30 @@ static ssize_t adxl372_get_fifo_watermark(struct device *dev,
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return sprintf(buf, "%d\n", st->watermark);
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}
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static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
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static IIO_CONST_ATTR(hwfifo_watermark_max,
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__stringify(ADXL372_FIFO_SIZE));
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static ssize_t hwfifo_watermark_min_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sysfs_emit(buf, "%s\n", "1");
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}
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static ssize_t hwfifo_watermark_max_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sysfs_emit(buf, "%s\n", __stringify(ADXL372_FIFO_SIZE));
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}
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static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
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static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
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static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
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adxl372_get_fifo_watermark, NULL, 0);
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static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
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adxl372_get_fifo_enabled, NULL, 0);
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|
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static const struct attribute *adxl372_fifo_attributes[] = {
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&iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
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&iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
|
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&iio_dev_attr_hwfifo_watermark_min.dev_attr.attr,
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&iio_dev_attr_hwfifo_watermark_max.dev_attr.attr,
|
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&iio_dev_attr_hwfifo_watermark.dev_attr.attr,
|
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&iio_dev_attr_hwfifo_enabled.dev_attr.attr,
|
||||
NULL,
|
||||
|
@ -925,17 +925,30 @@ static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = {
|
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{ }
|
||||
};
|
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|
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static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
|
||||
static IIO_CONST_ATTR(hwfifo_watermark_max,
|
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__stringify(BMC150_ACCEL_FIFO_LENGTH));
|
||||
static ssize_t hwfifo_watermark_min_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
return sysfs_emit(buf, "%s\n", "1");
|
||||
}
|
||||
|
||||
static ssize_t hwfifo_watermark_max_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
return sysfs_emit(buf, "%s\n", __stringify(BMC150_ACCEL_FIFO_LENGTH));
|
||||
}
|
||||
|
||||
static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
|
||||
static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
|
||||
static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
|
||||
bmc150_accel_get_fifo_state, NULL, 0);
|
||||
static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
|
||||
bmc150_accel_get_fifo_watermark, NULL, 0);
|
||||
|
||||
static const struct attribute *bmc150_accel_fifo_attributes[] = {
|
||||
&iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
|
||||
&iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_watermark_min.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_watermark_max.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_watermark.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_enabled.dev_attr.attr,
|
||||
NULL,
|
||||
|
@ -2193,17 +2193,30 @@ static ssize_t at91_adc_get_watermark(struct device *dev,
|
||||
return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
|
||||
}
|
||||
|
||||
static ssize_t hwfifo_watermark_min_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
return sysfs_emit(buf, "%s\n", "2");
|
||||
}
|
||||
|
||||
static ssize_t hwfifo_watermark_max_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
return sysfs_emit(buf, "%s\n", AT91_HWFIFO_MAX_SIZE_STR);
|
||||
}
|
||||
|
||||
static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
|
||||
at91_adc_get_fifo_state, NULL, 0);
|
||||
static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
|
||||
at91_adc_get_watermark, NULL, 0);
|
||||
|
||||
static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
|
||||
static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
|
||||
static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
|
||||
static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
|
||||
|
||||
static const struct attribute *at91_adc_fifo_attributes[] = {
|
||||
&iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
|
||||
&iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_watermark_min.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_watermark_max.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_watermark.dev_attr.attr,
|
||||
&iio_dev_attr_hwfifo_enabled.dev_attr.attr,
|
||||
NULL,
|
||||
|
@ -55,8 +55,9 @@
|
||||
/* Internal voltage reference in mV */
|
||||
#define MCP3911_INT_VREF_MV 1200
|
||||
|
||||
#define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff)
|
||||
#define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff)
|
||||
#define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff)
|
||||
#define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff)
|
||||
#define MCP3911_REG_MASK GENMASK(4, 1)
|
||||
|
||||
#define MCP3911_NUM_CHANNELS 2
|
||||
|
||||
@ -89,8 +90,8 @@ static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
|
||||
|
||||
be32_to_cpus(val);
|
||||
*val >>= ((4 - len) * 8);
|
||||
dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val,
|
||||
reg >> 1);
|
||||
dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val,
|
||||
FIELD_GET(MCP3911_REG_MASK, reg));
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -248,7 +249,7 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev,
|
||||
break;
|
||||
|
||||
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
|
||||
for (int i = 0; i < sizeof(mcp3911_osr_table); i++) {
|
||||
for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) {
|
||||
if (val == mcp3911_osr_table[i]) {
|
||||
val = FIELD_PREP(MCP3911_CONFIG_OSR, i);
|
||||
ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR,
|
||||
@ -496,7 +497,7 @@ static int mcp3911_probe(struct spi_device *spi)
|
||||
indio_dev->name,
|
||||
iio_device_id(indio_dev));
|
||||
if (!adc->trig)
|
||||
return PTR_ERR(adc->trig);
|
||||
return -ENOMEM;
|
||||
|
||||
adc->trig->ops = &mcp3911_trigger_ops;
|
||||
iio_trigger_set_drvdata(adc->trig, adc);
|
||||
|
@ -2086,18 +2086,19 @@ static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev,
|
||||
stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
|
||||
vin[1], scan_index, differential);
|
||||
|
||||
val = 0;
|
||||
ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val);
|
||||
/* st,min-sample-time-ns is optional */
|
||||
if (!ret) {
|
||||
stm32_adc_smpr_init(adc, channels[scan_index].channel, val);
|
||||
if (differential)
|
||||
stm32_adc_smpr_init(adc, vin[1], val);
|
||||
} else if (ret != -EINVAL) {
|
||||
if (ret && ret != -EINVAL) {
|
||||
dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n",
|
||||
ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
stm32_adc_smpr_init(adc, channels[scan_index].channel, val);
|
||||
if (differential)
|
||||
stm32_adc_smpr_init(adc, vin[1], val);
|
||||
|
||||
scan_index++;
|
||||
}
|
||||
|
||||
|
@ -858,7 +858,7 @@ static int tsl2583_probe(struct i2c_client *clientp,
|
||||
TSL2583_POWER_OFF_DELAY_MS);
|
||||
pm_runtime_use_autosuspend(&clientp->dev);
|
||||
|
||||
ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev);
|
||||
ret = iio_device_register(indio_dev);
|
||||
if (ret) {
|
||||
dev_err(&clientp->dev, "%s: iio registration failed\n",
|
||||
__func__);
|
||||
|
@ -1385,13 +1385,6 @@ static int ltc2983_setup(struct ltc2983_data *st, bool assign_iio)
|
||||
return ret;
|
||||
}
|
||||
|
||||
st->iio_chan = devm_kzalloc(&st->spi->dev,
|
||||
st->iio_channels * sizeof(*st->iio_chan),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (!st->iio_chan)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = regmap_update_bits(st->regmap, LTC2983_GLOBAL_CONFIG_REG,
|
||||
LTC2983_NOTCH_FREQ_MASK,
|
||||
LTC2983_NOTCH_FREQ(st->filter_notch_freq));
|
||||
@ -1514,6 +1507,12 @@ static int ltc2983_probe(struct spi_device *spi)
|
||||
gpiod_set_value_cansleep(gpio, 0);
|
||||
}
|
||||
|
||||
st->iio_chan = devm_kzalloc(&spi->dev,
|
||||
st->iio_channels * sizeof(*st->iio_chan),
|
||||
GFP_KERNEL);
|
||||
if (!st->iio_chan)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = ltc2983_setup(st, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
@ -152,7 +152,7 @@ static int gru_assign_asid(struct gru_state *gru)
|
||||
* Optionally, build an array of chars that contain the bit numbers allocated.
|
||||
*/
|
||||
static unsigned long reserve_resources(unsigned long *p, int n, int mmax,
|
||||
char *idx)
|
||||
signed char *idx)
|
||||
{
|
||||
unsigned long bits = 0;
|
||||
int i;
|
||||
@ -170,14 +170,14 @@ static unsigned long reserve_resources(unsigned long *p, int n, int mmax,
|
||||
}
|
||||
|
||||
unsigned long gru_reserve_cb_resources(struct gru_state *gru, int cbr_au_count,
|
||||
char *cbmap)
|
||||
signed char *cbmap)
|
||||
{
|
||||
return reserve_resources(&gru->gs_cbr_map, cbr_au_count, GRU_CBR_AU,
|
||||
cbmap);
|
||||
}
|
||||
|
||||
unsigned long gru_reserve_ds_resources(struct gru_state *gru, int dsr_au_count,
|
||||
char *dsmap)
|
||||
signed char *dsmap)
|
||||
{
|
||||
return reserve_resources(&gru->gs_dsr_map, dsr_au_count, GRU_DSR_AU,
|
||||
dsmap);
|
||||
|
@ -351,7 +351,7 @@ struct gru_thread_state {
|
||||
pid_t ts_tgid_owner; /* task that is using the
|
||||
context - for migration */
|
||||
short ts_user_blade_id;/* user selected blade */
|
||||
char ts_user_chiplet_id;/* user selected chiplet */
|
||||
signed char ts_user_chiplet_id;/* user selected chiplet */
|
||||
unsigned short ts_sizeavail; /* Pagesizes in use */
|
||||
int ts_tsid; /* thread that owns the
|
||||
structure */
|
||||
@ -364,11 +364,11 @@ struct gru_thread_state {
|
||||
required for contest */
|
||||
unsigned char ts_cbr_au_count;/* Number of CBR resources
|
||||
required for contest */
|
||||
char ts_cch_req_slice;/* CCH packet slice */
|
||||
char ts_blade; /* If >= 0, migrate context if
|
||||
signed char ts_cch_req_slice;/* CCH packet slice */
|
||||
signed char ts_blade; /* If >= 0, migrate context if
|
||||
ref from different blade */
|
||||
char ts_force_cch_reload;
|
||||
char ts_cbr_idx[GRU_CBR_AU];/* CBR numbers of each
|
||||
signed char ts_force_cch_reload;
|
||||
signed char ts_cbr_idx[GRU_CBR_AU];/* CBR numbers of each
|
||||
allocated CB */
|
||||
int ts_data_valid; /* Indicates if ts_gdata has
|
||||
valid data */
|
||||
@ -643,9 +643,9 @@ extern struct gru_thread_state *gru_alloc_gts(struct vm_area_struct *vma,
|
||||
int cbr_au_count, int dsr_au_count,
|
||||
unsigned char tlb_preload_count, int options, int tsid);
|
||||
extern unsigned long gru_reserve_cb_resources(struct gru_state *gru,
|
||||
int cbr_au_count, char *cbmap);
|
||||
int cbr_au_count, signed char *cbmap);
|
||||
extern unsigned long gru_reserve_ds_resources(struct gru_state *gru,
|
||||
int dsr_au_count, char *dsmap);
|
||||
int dsr_au_count, signed char *dsmap);
|
||||
extern vm_fault_t gru_fault(struct vm_fault *vmf);
|
||||
extern struct gru_mm_struct *gru_register_mmu_notifier(void);
|
||||
extern void gru_drop_mmu_notifier(struct gru_mm_struct *gms);
|
||||
|
@ -542,11 +542,10 @@ struct counter_array {
|
||||
#define DEFINE_COUNTER_ARRAY_CAPTURE(_name, _length) \
|
||||
DEFINE_COUNTER_ARRAY_U64(_name, _length)
|
||||
|
||||
#define DEFINE_COUNTER_ARRAY_POLARITY(_name, _enums, _length) \
|
||||
DEFINE_COUNTER_AVAILABLE(_name##_available, _enums); \
|
||||
#define DEFINE_COUNTER_ARRAY_POLARITY(_name, _available, _length) \
|
||||
struct counter_array _name = { \
|
||||
.type = COUNTER_COMP_SIGNAL_POLARITY, \
|
||||
.avail = &(_name##_available), \
|
||||
.avail = &(_available), \
|
||||
.length = (_length), \
|
||||
}
|
||||
|
||||
|
@ -547,6 +547,10 @@ static int calc_digits(int num)
|
||||
{
|
||||
int count = 0;
|
||||
|
||||
/* It takes a digit to represent zero */
|
||||
if (!num)
|
||||
return 1;
|
||||
|
||||
while (num != 0) {
|
||||
num /= 10;
|
||||
count++;
|
||||
|
Loading…
Reference in New Issue
Block a user