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PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()

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Make use of regmap_read_poll_timeout() to simplify
imx7d_pcie_wait_for_phy_pll_lock(). No functional change intended.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
This commit is contained in:
Andrey Smirnov
2019-04-14 17:46:22 -07:00
committed by Lorenzo Pieralisi
parent 9e98c678c2
commit 9e303be2e5
1 changed files with 7 additions and 14 deletions
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19
drivers/pci/controller/dwc/pci-imx6.c
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@@ -89,9 +89,8 @@ struct imx6_pcie {
}; };
/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
#define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
#define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
/* PCIe Root Complex registers (memory-mapped) */ /* PCIe Root Complex registers (memory-mapped) */
#define PCIE_RC_IMX6_MSI_CAP 0x50 #define PCIE_RC_IMX6_MSI_CAP 0x50
@@ -488,19 +487,13 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
{ {
u32 val; u32 val;
unsigned int retries;
struct device *dev = imx6_pcie->pci->dev; struct device *dev = imx6_pcie->pci->dev;
for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) { if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val); IOMUXC_GPR22, val,
val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED) PHY_PLL_LOCK_WAIT_USLEEP_MAX,
return; PHY_PLL_LOCK_WAIT_TIMEOUT))
usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
PHY_PLL_LOCK_WAIT_USLEEP_MAX);
}
dev_err(dev, "PCIe PLL lock timeout\n"); dev_err(dev, "PCIe PLL lock timeout\n");
} }