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ARM: dts: sunxi: Add missing watchdog clocks

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The watchdog has a clock on all our SoCs, but it wasn't always listed.
Add it to the devicetree where it's missing.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Maxime Ripard
2019-08-21 16:38:35 +02:00
parent 89d1e51462
commit 9e1975f0bc
10 changed files with 11 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/sun4i-a10.dtsi
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@@ -816,6 +816,7 @@
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <24>; interrupts = <24>;
clocks = <&osc24M>;
}; };
rtc: rtc@1c20d00 { rtc: rtc@1c20d00 {

1
arch/arm/boot/dts/sun5i.dtsi
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@@ -601,6 +601,7 @@
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <24>; interrupts = <24>;
clocks = <&osc24M>;
}; };
ir0: ir@1c21800 { ir0: ir@1c21800 {

1
arch/arm/boot/dts/sun6i-a31.dtsi
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@@ -745,6 +745,7 @@
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>; reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
spdif: spdif@1c21000 { spdif: spdif@1c21000 {

1
arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -1141,6 +1141,7 @@
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
rtc: rtc@1c20d00 { rtc: rtc@1c20d00 {

1
arch/arm/boot/dts/sun8i-a23-a33.dtsi
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@@ -452,6 +452,7 @@
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>; reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
pwm: pwm@1c21400 { pwm: pwm@1c21400 {

1
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@@ -405,6 +405,7 @@
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
uart0: serial@1c28000 { uart0: serial@1c28000 {

1
arch/arm/boot/dts/sun8i-v3s.dtsi
View File

@@ -339,6 +339,7 @@
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>; reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
lradc: lradc@1c22800 { lradc: lradc@1c22800 {

1
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@@ -574,6 +574,7 @@
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>; reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
spdif: spdif@1c21000 { spdif: spdif@1c21000 {

1
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@@ -1169,6 +1169,7 @@
"allwinner,sun6i-a31-wdt"; "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>; reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
}; };
}; };

2
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -217,6 +217,7 @@
"allwinner,sun6i-a31-wdt"; "allwinner,sun6i-a31-wdt";
reg = <0x030090a0 0x20>; reg = <0x030090a0 0x20>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
/* Broken on some H6 boards */ /* Broken on some H6 boards */
status = "disabled"; status = "disabled";
}; };
@@ -727,6 +728,7 @@
"allwinner,sun6i-a31-wdt"; "allwinner,sun6i-a31-wdt";
reg = <0x07020400 0x20>; reg = <0x07020400 0x20>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
}; };
r_intc: interrupt-controller@7021000 { r_intc: interrupt-controller@7021000 {