forked from Minki/linux
x86/insn: Add AMX instructions to the x86 instruction decoder
The x86 instruction decoder is used for both kernel instructions and user space instructions (e.g. uprobes, perf tools Intel PT), so it is good to update it with new instructions. Add AMX instructions to the x86 instruction decoder. Reference: Intel Architecture Instruction Set Extensions and Future Features Programming Reference May 2021 Document Number: 319433-044 Example using perf tools' x86 instruction decoder test: $ INSN='ldtilecfg\|sttilecfg\|tdpbf16ps\|tdpbssd\|' $ INSN+='tdpbsud\|tdpbusd\|'tdpbuud\|tileloadd\|' $ INSN+='tileloaddt1\|tilerelease\|tilestored\|tilezero' $ perf test -v "x86 instruction decoder" |& grep -i $INSN Decoded ok: c4 e2 78 49 04 c8 ldtilecfg (%rax,%rcx,8) Decoded ok: c4 c2 78 49 04 c8 ldtilecfg (%r8,%rcx,8) Decoded ok: c4 e2 79 49 04 c8 sttilecfg (%rax,%rcx,8) Decoded ok: c4 c2 79 49 04 c8 sttilecfg (%r8,%rcx,8) Decoded ok: c4 e2 7a 5c d1 tdpbf16ps %tmm0,%tmm1,%tmm2 Decoded ok: c4 e2 7b 5e d1 tdpbssd %tmm0,%tmm1,%tmm2 Decoded ok: c4 e2 7a 5e d1 tdpbsud %tmm0,%tmm1,%tmm2 Decoded ok: c4 e2 79 5e d1 tdpbusd %tmm0,%tmm1,%tmm2 Decoded ok: c4 e2 78 5e d1 tdpbuud %tmm0,%tmm1,%tmm2 Decoded ok: c4 e2 7b 4b 0c c8 tileloadd (%rax,%rcx,8),%tmm1 Decoded ok: c4 c2 7b 4b 14 c8 tileloadd (%r8,%rcx,8),%tmm2 Decoded ok: c4 e2 79 4b 0c c8 tileloaddt1 (%rax,%rcx,8),%tmm1 Decoded ok: c4 c2 79 4b 14 c8 tileloaddt1 (%r8,%rcx,8),%tmm2 Decoded ok: c4 e2 78 49 c0 tilerelease Decoded ok: c4 e2 7a 4b 0c c8 tilestored %tmm1,(%rax,%rcx,8) Decoded ok: c4 c2 7a 4b 14 c8 tilestored %tmm2,(%r8,%rcx,8) Decoded ok: c4 e2 7b 49 c0 tilezero %tmm0 Decoded ok: c4 e2 7b 49 f8 tilezero %tmm7 Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Arnaldo Carvalho de Melo <acme@redhat.com> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Link: https://lore.kernel.org/r/20211202095029.2165714-3-adrian.hunter@intel.com
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@ -690,7 +690,10 @@ AVXcode: 2
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45: vpsrlvd/q Vx,Hx,Wx (66),(v)
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46: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo)
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47: vpsllvd/q Vx,Hx,Wx (66),(v)
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# Skip 0x48-0x4b
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# Skip 0x48
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49: TILERELEASE (v1),(000),(11B) | LDTILECFG Mtc (v1)(000) | STTILECFG Mtc (66),(v1),(000) | TILEZERO Vt (F2),(v1),(11B)
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# Skip 0x4a
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4b: TILELOADD Vt,Wsm (F2),(v1) | TILELOADDT1 Vt,Wsm (66),(v1) | TILESTORED Wsm,Vt (F3),(v)
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4c: vrcp14ps/d Vpd,Wpd (66),(ev)
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4d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev)
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4e: vrsqrt14ps/d Vpd,Wpd (66),(ev)
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@ -705,7 +708,10 @@ AVXcode: 2
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59: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo)
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5a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo)
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5b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev)
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# Skip 0x5c-0x61
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5c: TDPBF16PS Vt,Wt,Ht (F3),(v1)
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# Skip 0x5d
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5e: TDPBSSD Vt,Wt,Ht (F2),(v1) | TDPBSUD Vt,Wt,Ht (F3),(v1) | TDPBUSD Vt,Wt,Ht (66),(v1) | TDPBUUD Vt,Wt,Ht (v1)
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# Skip 0x5f-0x61
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62: vpexpandb/w Vx,Wx (66),(ev)
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63: vpcompressb/w Wx,Vx (66),(ev)
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64: vpblendmd/q Vx,Hx,Wx (66),(ev)
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@ -690,7 +690,10 @@ AVXcode: 2
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45: vpsrlvd/q Vx,Hx,Wx (66),(v)
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46: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo)
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47: vpsllvd/q Vx,Hx,Wx (66),(v)
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# Skip 0x48-0x4b
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# Skip 0x48
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49: TILERELEASE (v1),(000),(11B) | LDTILECFG Mtc (v1)(000) | STTILECFG Mtc (66),(v1),(000) | TILEZERO Vt (F2),(v1),(11B)
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# Skip 0x4a
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4b: TILELOADD Vt,Wsm (F2),(v1) | TILELOADDT1 Vt,Wsm (66),(v1) | TILESTORED Wsm,Vt (F3),(v)
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4c: vrcp14ps/d Vpd,Wpd (66),(ev)
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4d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev)
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4e: vrsqrt14ps/d Vpd,Wpd (66),(ev)
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@ -705,7 +708,10 @@ AVXcode: 2
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59: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo)
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5a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo)
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5b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev)
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# Skip 0x5c-0x61
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5c: TDPBF16PS Vt,Wt,Ht (F3),(v1)
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# Skip 0x5d
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5e: TDPBSSD Vt,Wt,Ht (F2),(v1) | TDPBSUD Vt,Wt,Ht (F3),(v1) | TDPBUSD Vt,Wt,Ht (66),(v1) | TDPBUUD Vt,Wt,Ht (v1)
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# Skip 0x5f-0x61
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62: vpexpandb/w Vx,Wx (66),(ev)
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63: vpcompressb/w Wx,Vx (66),(ev)
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64: vpblendmd/q Vx,Hx,Wx (66),(ev)
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