forked from Minki/linux
[SCSI] qla2xxx: Support for loading Unified ROM Image (URI) format firmware file.
Used bootloder address from FLT while loading FW from flash as well. Signed-off-by: Giridhar Malavali <giridhar.malavali@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
Harish Zunjarrao
James Bottomley
parent
b0cd579cde
commit
9c2b297572
@ -2788,6 +2788,9 @@ struct qla_hw_data {
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uint16_t gbl_dsd_avail;
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struct list_head gbl_dsd_list;
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#define NUM_DSD_CHAIN 4096
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uint8_t fw_type;
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__le32 file_prd_off; /* File firmware product offset */
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};
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/*
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@ -1407,7 +1407,8 @@ qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
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{
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int i;
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long size = 0;
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long flashaddr = BOOTLD_START, memaddr = BOOTLD_START;
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long flashaddr = ha->flt_region_bootload << 2;
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long memaddr = BOOTLD_START;
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u64 data;
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u32 high, low;
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size = (IMAGE_START - BOOTLD_START) / 8;
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@ -1677,6 +1678,94 @@ qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
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return ret;
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}
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static struct qla82xx_uri_table_desc *
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qla82xx_get_table_desc(const u8 *unirom, int section)
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{
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uint32_t i;
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struct qla82xx_uri_table_desc *directory =
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(struct qla82xx_uri_table_desc *)&unirom[0];
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__le32 offset;
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__le32 tab_type;
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__le32 entries = cpu_to_le32(directory->num_entries);
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for (i = 0; i < entries; i++) {
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offset = cpu_to_le32(directory->findex) +
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(i * cpu_to_le32(directory->entry_size));
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tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
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if (tab_type == section)
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return (struct qla82xx_uri_table_desc *)&unirom[offset];
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}
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return NULL;
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}
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static struct qla82xx_uri_data_desc *
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qla82xx_get_data_desc(struct qla_hw_data *ha,
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u32 section, u32 idx_offset)
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{
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const u8 *unirom = ha->hablob->fw->data;
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int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
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struct qla82xx_uri_table_desc *tab_desc = NULL;
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__le32 offset;
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tab_desc = qla82xx_get_table_desc(unirom, section);
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if (!tab_desc)
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return NULL;
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offset = cpu_to_le32(tab_desc->findex) +
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(cpu_to_le32(tab_desc->entry_size) * idx);
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return (struct qla82xx_uri_data_desc *)&unirom[offset];
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}
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static u8 *
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qla82xx_get_bootld_offset(struct qla_hw_data *ha)
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{
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u32 offset = BOOTLD_START;
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struct qla82xx_uri_data_desc *uri_desc = NULL;
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if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
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uri_desc = qla82xx_get_data_desc(ha,
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QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
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if (uri_desc)
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offset = cpu_to_le32(uri_desc->findex);
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}
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return (u8 *)&ha->hablob->fw->data[offset];
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}
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static __le32
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qla82xx_get_fw_size(struct qla_hw_data *ha)
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{
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struct qla82xx_uri_data_desc *uri_desc = NULL;
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if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
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uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
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QLA82XX_URI_FIRMWARE_IDX_OFF);
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if (uri_desc)
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return cpu_to_le32(uri_desc->size);
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}
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return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
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}
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static u8 *
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qla82xx_get_fw_offs(struct qla_hw_data *ha)
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{
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u32 offset = IMAGE_START;
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struct qla82xx_uri_data_desc *uri_desc = NULL;
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if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
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uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
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QLA82XX_URI_FIRMWARE_IDX_OFF);
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if (uri_desc)
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offset = cpu_to_le32(uri_desc->findex);
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}
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return (u8 *)&ha->hablob->fw->data[offset];
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}
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/* PCI related functions */
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char *
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qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str)
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@ -1878,19 +1967,19 @@ int qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
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size = (IMAGE_START - BOOTLD_START) / 8;
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ptr64 = (u64 *)&ha->hablob->fw->data[BOOTLD_START];
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ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
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flashaddr = BOOTLD_START;
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for (i = 0; i < size; i++) {
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data = cpu_to_le64(ptr64[i]);
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qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8);
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if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
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return -EIO;
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flashaddr += 8;
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}
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size = *(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET];
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size = (__force u32)cpu_to_le32(size) / 8;
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ptr64 = (u64 *)&ha->hablob->fw->data[IMAGE_START];
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flashaddr = FLASH_ADDR_START;
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size = (__force u32)qla82xx_get_fw_size(ha) / 8;
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ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
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for (i = 0; i < size; i++) {
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data = cpu_to_le64(ptr64[i]);
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@ -1899,19 +1988,88 @@ int qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
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return -EIO;
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flashaddr += 8;
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}
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udelay(100);
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/* Write a magic value to CAMRAM register
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* at a specified offset to indicate
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* that all data is written and
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* ready for firmware to initialize.
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*/
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qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), 0x12345678);
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qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
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read_lock(&ha->hw_lock);
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if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
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qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
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} else
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d);
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read_unlock(&ha->hw_lock);
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return 0;
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}
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static int
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qla82xx_set_product_offset(struct qla_hw_data *ha)
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{
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struct qla82xx_uri_table_desc *ptab_desc = NULL;
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const uint8_t *unirom = ha->hablob->fw->data;
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uint32_t i;
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__le32 entries;
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__le32 flags, file_chiprev, offset;
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uint8_t chiprev = ha->chip_revision;
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/* Hardcoding mn_present flag for P3P */
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int mn_present = 0;
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uint32_t flagbit;
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ptab_desc = qla82xx_get_table_desc(unirom,
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QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
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if (!ptab_desc)
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return -1;
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entries = cpu_to_le32(ptab_desc->num_entries);
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for (i = 0; i < entries; i++) {
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offset = cpu_to_le32(ptab_desc->findex) +
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(i * cpu_to_le32(ptab_desc->entry_size));
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flags = cpu_to_le32(*((int *)&unirom[offset] +
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QLA82XX_URI_FLAGS_OFF));
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file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
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QLA82XX_URI_CHIP_REV_OFF));
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flagbit = mn_present ? 1 : 2;
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if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
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ha->file_prd_off = offset;
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return 0;
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}
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}
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return -1;
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}
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int
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qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
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{
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__le32 val;
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uint32_t min_size;
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struct qla_hw_data *ha = vha->hw;
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const struct firmware *fw = ha->hablob->fw;
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ha->fw_type = fw_type;
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if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
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if (qla82xx_set_product_offset(ha))
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return -EINVAL;
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min_size = QLA82XX_URI_FW_MIN_SIZE;
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} else {
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val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
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if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
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return -EINVAL;
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min_size = QLA82XX_FW_MIN_SIZE;
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}
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if (fw->size < min_size)
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return -EINVAL;
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return 0;
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}
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@ -2470,6 +2628,18 @@ try_blob_fw:
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goto fw_load_failed;
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}
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/* Validating firmware blob */
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if (qla82xx_validate_firmware_blob(vha,
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QLA82XX_FLASH_ROMIMAGE)) {
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/* Fallback to URI format */
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if (qla82xx_validate_firmware_blob(vha,
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QLA82XX_UNIFIED_ROMIMAGE)) {
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qla_printk(KERN_ERR, ha,
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"No valid firmware image found!!!");
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return QLA_FUNCTION_FAILED;
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}
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}
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if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
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qla_printk(KERN_ERR, ha,
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"%s: Firmware loaded successfully "
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@ -773,13 +773,48 @@ struct qla82xx_legacy_intr_set {
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.pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
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}
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#define BRDCFG_START 0x4000
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#define BOOTLD_START 0x10000
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#define IMAGE_START 0x100000
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#define FLASH_ADDR_START 0x43000
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/* Magic number to let user know flash is programmed */
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#define QLA82XX_BDINFO_MAGIC 0x12345678
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#define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128)
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#define FW_SIZE_OFFSET (0x3e840c)
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#define QLA82XX_FW_MIN_SIZE 0x3fffff
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/* UNIFIED ROMIMAGE START */
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#define QLA82XX_URI_FW_MIN_SIZE 0xc8000
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#define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0
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#define QLA82XX_URI_DIR_SECT_BOOTLD 0x6
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#define QLA82XX_URI_DIR_SECT_FW 0x7
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/* Offsets */
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#define QLA82XX_URI_CHIP_REV_OFF 10
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#define QLA82XX_URI_FLAGS_OFF 11
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#define QLA82XX_URI_BIOS_VERSION_OFF 12
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#define QLA82XX_URI_BOOTLD_IDX_OFF 27
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#define QLA82XX_URI_FIRMWARE_IDX_OFF 29
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struct qla82xx_uri_table_desc{
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uint32_t findex;
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uint32_t num_entries;
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uint32_t entry_size;
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uint32_t reserved[5];
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};
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struct qla82xx_uri_data_desc{
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uint32_t findex;
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uint32_t size;
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uint32_t reserved[5];
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};
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/* UNIFIED ROMIMAGE END */
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#define QLA82XX_UNIFIED_ROMIMAGE 3
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#define QLA82XX_FLASH_ROMIMAGE 4
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#define QLA82XX_UNKNOWN_ROMIMAGE 0xff
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#define QLA82XX_IS_REVISION_P3PLUS(_rev_) ((_rev_) >= 0x50)
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#define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
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