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Merge branch 'davinci-next-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci into devel-stable

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This commit is contained in:
Russell King 2011-03-15 15:41:15 +00:00
commit 9b963f32c3
12 changed files with 1082 additions and 6 deletions
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8
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -440,11 +440,6 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
gpio_request(gpio + 7, "nCF_SEL");
gpio_direction_output(gpio + 7, 1);
/* irlml6401 switches over 1A, in under 8 msec;
* now it can be managed by nDRV_VBUS ...
*/
davinci_setup_usb(1000, 8);
return 0;
}
@ -705,6 +700,9 @@ static __init void davinci_evm_init(void)
davinci_serial_init(&uart_config);
dm644x_init_asp(&dm644x_evm_snd_data);
/* irlml6401 switches over 1A, in under 8 msec */
davinci_setup_usb(1000, 8);
soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
/* Register the fixup for PHY on DaVinci */
phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,

57
arch/arm/mach-davinci/board-tnetv107x-evm.c
View File

@ -25,6 +25,7 @@
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@ -37,6 +38,7 @@
#define EVM_MMC_WP_GPIO 21
#define EVM_MMC_CD_GPIO 24
#define EVM_SPI_CS_GPIO 54
static int initialize_gpio(int gpio, char *desc)
{
@ -99,6 +101,12 @@ static const short uart1_pins[] __initdata = {
-1
};
static const short ssp_pins[] __initdata = {
TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
TNETV107X_SSP1_3, -1
};
static struct mtd_partition nand_partitions[] = {
/* bootloader (U-Boot, etc) in first 12 sectors */
{
@ -196,19 +204,68 @@ static struct matrix_keypad_platform_data keypad_config = {
.no_autorepeat = 0,
};
static void spi_select_device(int cs)
{
static int gpio;
if (!gpio) {
int ret;
ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
if (ret < 0) {
pr_err("cannot open spi chipsel gpio\n");
gpio = -ENOSYS;
return;
} else {
gpio = EVM_SPI_CS_GPIO;
gpio_direction_output(gpio, 0);
}
}
if (gpio < 0)
return;
return gpio_set_value(gpio, cs ? 1 : 0);
}
static struct ti_ssp_spi_data spi_master_data = {
.num_cs = 2,
.select = spi_select_device,
.iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) |
SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) |
SSP_INPUT_SEL(3),
};
static struct ti_ssp_data ssp_config = {
.out_clock = 250 * 1000,
.dev_data = {
[1] = {
.dev_name = "ti-ssp-spi",
.pdata = &spi_master_data,
.pdata_size = sizeof(spi_master_data),
},
},
};
static struct tnetv107x_device_info evm_device_info __initconst = {
.serial_config = &serial_config,
.mmc_config[1] = &mmc_config, /* controller 1 */
.nand_config[0] = &nand_config, /* chip select 0 */
.keypad_config = &keypad_config,
.ssp_config = &ssp_config,
};
static struct spi_board_info spi_info[] __initconst = {
};
static __init void tnetv107x_evm_board_init(void)
{
davinci_cfg_reg_list(sdio1_pins);
davinci_cfg_reg_list(uart1_pins);
davinci_cfg_reg_list(ssp_pins);
tnetv107x_devices_init(&evm_device_info);
spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
}
#ifdef CONFIG_SERIAL_8250_CONSOLE

25
arch/arm/mach-davinci/devices-tnetv107x.c
View File

@ -35,6 +35,7 @@
#define TNETV107X_SDIO0_BASE 0x08088700
#define TNETV107X_SDIO1_BASE 0x08088800
#define TNETV107X_KEYPAD_BASE 0x08088a00
#define TNETV107X_SSP_BASE 0x08088c00
#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
@ -342,6 +343,25 @@ static struct platform_device tsc_device = {
.resource = tsc_resources,
};
static struct resource ssp_resources[] = {
{
.start = TNETV107X_SSP_BASE,
.end = TNETV107X_SSP_BASE + 0x1ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_TNETV107X_SSP,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ssp_device = {
.name = "ti-ssp",
.id = -1,
.num_resources = ARRAY_SIZE(ssp_resources),
.resource = ssp_resources,
};
void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
{
int i, error;
@ -380,4 +400,9 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
keypad_device.dev.platform_data = info->keypad_config;
platform_device_register(&keypad_device);
}
if (info->ssp_config) {
ssp_device.dev.platform_data = info->ssp_config;
platform_device_register(&ssp_device);
}
}

2
arch/arm/mach-davinci/include/mach/tnetv107x.h
View File

@ -34,6 +34,7 @@
#include <linux/serial_8250.h>
#include <linux/input/matrix_keypad.h>
#include <linux/mfd/ti_ssp.h>
#include <mach/mmc.h>
#include <mach/nand.h>
@ -44,6 +45,7 @@ struct tnetv107x_device_info {
struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
struct matrix_keypad_platform_data *keypad_config;
struct ti_ssp_data *ssp_config;
};
extern struct platform_device tnetv107x_wdt_device;

2
arch/arm/mach-davinci/tnetv107x.c
View File

@ -278,7 +278,7 @@ static struct clk_lookup clks[] = {
CLK(NULL, "timer1", &clk_timer1),
CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm),
CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp),
CLK("ti-ssp.0", NULL, &clk_ssp),
CLK("ti-ssp", NULL, &clk_ssp),
CLK(NULL, "clk_tdm0", &clk_tdm0),
CLK(NULL, "clk_vlynq", &clk_vlynq),
CLK(NULL, "clk_mcdma", &clk_mcdma),

11
drivers/mfd/Kconfig
View File

@ -81,6 +81,17 @@ config MFD_DM355EVM_MSP
boards. MSP430 firmware manages resets and power sequencing,
inputs from buttons and the IR remote, LEDs, an RTC, and more.
config MFD_TI_SSP
tristate "TI Sequencer Serial Port support"
depends on ARCH_DAVINCI_TNETV107X
select MFD_CORE
---help---
Say Y here if you want support for the Sequencer Serial Port
in a Texas Instruments TNETV107X SoC.
To compile this driver as a module, choose M here: the
module will be called ti-ssp.
config HTC_EGPIO
bool "HTC EGPIO support"
depends on GENERIC_HARDIRQS && GPIOLIB && ARM

1
drivers/mfd/Makefile
View File

@ -14,6 +14,7 @@ obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o
obj-$(CONFIG_MFD_DAVINCI_VOICECODEC) += davinci_voicecodec.o
obj-$(CONFIG_MFD_DM355EVM_MSP) += dm355evm_msp.o
obj-$(CONFIG_MFD_TI_SSP) += ti-ssp.o
obj-$(CONFIG_MFD_STMPE) += stmpe.o
obj-$(CONFIG_MFD_TC3589X) += tc3589x.o

476
drivers/mfd/ti-ssp.c Normal file
View File

@ -0,0 +1,476 @@
/*
* Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/wait.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ti_ssp.h>
/* Register Offsets */
#define REG_REV 0x00
#define REG_IOSEL_1 0x04
#define REG_IOSEL_2 0x08
#define REG_PREDIV 0x0c
#define REG_INTR_ST 0x10
#define REG_INTR_EN 0x14
#define REG_TEST_CTRL 0x18
/* Per port registers */
#define PORT_CFG_2 0x00
#define PORT_ADDR 0x04
#define PORT_DATA 0x08
#define PORT_CFG_1 0x0c
#define PORT_STATE 0x10
#define SSP_PORT_CONFIG_MASK (SSP_EARLY_DIN | SSP_DELAY_DOUT)
#define SSP_PORT_CLKRATE_MASK 0x0f
#define SSP_SEQRAM_WR_EN BIT(4)
#define SSP_SEQRAM_RD_EN BIT(5)
#define SSP_START BIT(15)
#define SSP_BUSY BIT(10)
#define SSP_PORT_ASL BIT(7)
#define SSP_PORT_CFO1 BIT(6)
#define SSP_PORT_SEQRAM_SIZE 32
static const int ssp_port_base[] = {0x040, 0x080};
static const int ssp_port_seqram[] = {0x100, 0x180};
struct ti_ssp {
struct resource *res;
struct device *dev;
void __iomem *regs;
spinlock_t lock;
struct clk *clk;
int irq;
wait_queue_head_t wqh;
/*
* Some of the iosel2 register bits always read-back as 0, we need to
* remember these values so that we don't clobber previously set
* values.
*/
u32 iosel2;
};
static inline struct ti_ssp *dev_to_ssp(struct device *dev)
{
return dev_get_drvdata(dev->parent);
}
static inline int dev_to_port(struct device *dev)
{
return to_platform_device(dev)->id;
}
/* Register Access Helpers, rmw() functions need to run locked */
static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
{
return __raw_readl(ssp->regs + reg);
}
static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
{
__raw_writel(val, ssp->regs + reg);
}
static inline void ssp_rmw(struct ti_ssp *ssp, int reg, u32 mask, u32 bits)
{
ssp_write(ssp, reg, (ssp_read(ssp, reg) & ~mask) | bits);
}
static inline u32 ssp_port_read(struct ti_ssp *ssp, int port, int reg)
{
return ssp_read(ssp, ssp_port_base[port] + reg);
}
static inline void ssp_port_write(struct ti_ssp *ssp, int port, int reg,
u32 val)
{
ssp_write(ssp, ssp_port_base[port] + reg, val);
}
static inline void ssp_port_rmw(struct ti_ssp *ssp, int port, int reg,
u32 mask, u32 bits)
{
ssp_rmw(ssp, ssp_port_base[port] + reg, mask, bits);
}
static inline void ssp_port_clr_bits(struct ti_ssp *ssp, int port, int reg,
u32 bits)
{
ssp_port_rmw(ssp, port, reg, bits, 0);
}
static inline void ssp_port_set_bits(struct ti_ssp *ssp, int port, int reg,
u32 bits)
{
ssp_port_rmw(ssp, port, reg, 0, bits);
}
/* Called to setup port clock mode, caller must hold ssp->lock */
static int __set_mode(struct ti_ssp *ssp, int port, int mode)
{
mode &= SSP_PORT_CONFIG_MASK;
ssp_port_rmw(ssp, port, PORT_CFG_1, SSP_PORT_CONFIG_MASK, mode);
return 0;
}
int ti_ssp_set_mode(struct device *dev, int mode)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
int ret;
spin_lock(&ssp->lock);
ret = __set_mode(ssp, port, mode);
spin_unlock(&ssp->lock);
return ret;
}
EXPORT_SYMBOL(ti_ssp_set_mode);
/* Called to setup iosel2, caller must hold ssp->lock */
static void __set_iosel2(struct ti_ssp *ssp, u32 mask, u32 val)
{
ssp->iosel2 = (ssp->iosel2 & ~mask) | val;
ssp_write(ssp, REG_IOSEL_2, ssp->iosel2);
}
/* Called to setup port iosel, caller must hold ssp->lock */
static void __set_iosel(struct ti_ssp *ssp, int port, u32 iosel)
{
unsigned val, shift = port ? 16 : 0;
/* IOSEL1 gets the least significant 16 bits */
val = ssp_read(ssp, REG_IOSEL_1);
val &= 0xffff << (port ? 0 : 16);
val |= (iosel & 0xffff) << (port ? 16 : 0);
ssp_write(ssp, REG_IOSEL_1, val);
/* IOSEL2 gets the most significant 16 bits */
val = (iosel >> 16) & 0x7;
__set_iosel2(ssp, 0x7 << shift, val << shift);
}
int ti_ssp_set_iosel(struct device *dev, u32 iosel)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
spin_lock(&ssp->lock);
__set_iosel(ssp, port, iosel);
spin_unlock(&ssp->lock);
return 0;
}
EXPORT_SYMBOL(ti_ssp_set_iosel);
int ti_ssp_load(struct device *dev, int offs, u32* prog, int len)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
int i;
if (len > SSP_PORT_SEQRAM_SIZE)
return -ENOSPC;
spin_lock(&ssp->lock);
/* Enable SeqRAM access */
ssp_port_set_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
/* Copy code */
for (i = 0; i < len; i++) {
__raw_writel(prog[i], ssp->regs + offs + 4*i +
ssp_port_seqram[port]);
}
/* Disable SeqRAM access */
ssp_port_clr_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
spin_unlock(&ssp->lock);
return 0;
}
EXPORT_SYMBOL(ti_ssp_load);
int ti_ssp_raw_read(struct device *dev)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
int shift = port ? 27 : 11;
return (ssp_read(ssp, REG_IOSEL_2) >> shift) & 0xf;
}
EXPORT_SYMBOL(ti_ssp_raw_read);
int ti_ssp_raw_write(struct device *dev, u32 val)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev), shift;
spin_lock(&ssp->lock);
shift = port ? 22 : 6;
val &= 0xf;
__set_iosel2(ssp, 0xf << shift, val << shift);
spin_unlock(&ssp->lock);
return 0;
}
EXPORT_SYMBOL(ti_ssp_raw_write);
static inline int __xfer_done(struct ti_ssp *ssp, int port)
{
return !(ssp_port_read(ssp, port, PORT_CFG_1) & SSP_BUSY);
}
int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
int ret;
if (pc & ~(0x3f))
return -EINVAL;
/* Grab ssp->lock to serialize rmw on ssp registers */
spin_lock(&ssp->lock);
ssp_port_write(ssp, port, PORT_ADDR, input >> 16);
ssp_port_write(ssp, port, PORT_DATA, input & 0xffff);
ssp_port_rmw(ssp, port, PORT_CFG_1, 0x3f, pc);
/* grab wait queue head lock to avoid race with the isr */
spin_lock_irq(&ssp->wqh.lock);
/* kick off sequence execution in hardware */
ssp_port_set_bits(ssp, port, PORT_CFG_1, SSP_START);
/* drop ssp lock; no register writes beyond this */
spin_unlock(&ssp->lock);
ret = wait_event_interruptible_locked_irq(ssp->wqh,
__xfer_done(ssp, port));
spin_unlock_irq(&ssp->wqh.lock);
if (ret < 0)
return ret;
if (output) {
*output = (ssp_port_read(ssp, port, PORT_ADDR) << 16) |
(ssp_port_read(ssp, port, PORT_DATA) & 0xffff);
}
ret = ssp_port_read(ssp, port, PORT_STATE) & 0x3f; /* stop address */
return ret;
}
EXPORT_SYMBOL(ti_ssp_run);
static irqreturn_t ti_ssp_interrupt(int irq, void *dev_data)
{
struct ti_ssp *ssp = dev_data;
spin_lock(&ssp->wqh.lock);
ssp_write(ssp, REG_INTR_ST, 0x3);
wake_up_locked(&ssp->wqh);
spin_unlock(&ssp->wqh.lock);
return IRQ_HANDLED;
}
static int __devinit ti_ssp_probe(struct platform_device *pdev)
{
static struct ti_ssp *ssp;
const struct ti_ssp_data *pdata = pdev->dev.platform_data;
int error = 0, prediv = 0xff, id;
unsigned long sysclk;
struct device *dev = &pdev->dev;
struct mfd_cell cells[2];
ssp = kzalloc(sizeof(*ssp), GFP_KERNEL);
if (!ssp) {
dev_err(dev, "cannot allocate device info\n");
return -ENOMEM;
}
ssp->dev = dev;
dev_set_drvdata(dev, ssp);
ssp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!ssp->res) {
error = -ENODEV;
dev_err(dev, "cannot determine register area\n");
goto error_res;
}
if (!request_mem_region(ssp->res->start, resource_size(ssp->res),
pdev->name)) {
error = -ENOMEM;
dev_err(dev, "cannot claim register memory\n");
goto error_res;
}
ssp->regs = ioremap(ssp->res->start, resource_size(ssp->res));
if (!ssp->regs) {
error = -ENOMEM;
dev_err(dev, "cannot map register memory\n");
goto error_map;
}
ssp->clk = clk_get(dev, NULL);
if (IS_ERR(ssp->clk)) {
error = PTR_ERR(ssp->clk);
dev_err(dev, "cannot claim device clock\n");
goto error_clk;
}
ssp->irq = platform_get_irq(pdev, 0);
if (ssp->irq < 0) {
error = -ENODEV;
dev_err(dev, "unknown irq\n");
goto error_irq;
}
error = request_threaded_irq(ssp->irq, NULL, ti_ssp_interrupt, 0,
dev_name(dev), ssp);
if (error < 0) {
dev_err(dev, "cannot acquire irq\n");
goto error_irq;
}
spin_lock_init(&ssp->lock);
init_waitqueue_head(&ssp->wqh);
/* Power on and initialize SSP */
error = clk_enable(ssp->clk);
if (error) {
dev_err(dev, "cannot enable device clock\n");
goto error_enable;
}
/* Reset registers to a sensible known state */
ssp_write(ssp, REG_IOSEL_1, 0);
ssp_write(ssp, REG_IOSEL_2, 0);
ssp_write(ssp, REG_INTR_EN, 0x3);
ssp_write(ssp, REG_INTR_ST, 0x3);
ssp_write(ssp, REG_TEST_CTRL, 0);
ssp_port_write(ssp, 0, PORT_CFG_1, SSP_PORT_ASL);
ssp_port_write(ssp, 1, PORT_CFG_1, SSP_PORT_ASL);
ssp_port_write(ssp, 0, PORT_CFG_2, SSP_PORT_CFO1);
ssp_port_write(ssp, 1, PORT_CFG_2, SSP_PORT_CFO1);
sysclk = clk_get_rate(ssp->clk);
if (pdata && pdata->out_clock)
prediv = (sysclk / pdata->out_clock) - 1;
prediv = clamp(prediv, 0, 0xff);
ssp_rmw(ssp, REG_PREDIV, 0xff, prediv);
memset(cells, 0, sizeof(cells));
for (id = 0; id < 2; id++) {
const struct ti_ssp_dev_data *data = &pdata->dev_data[id];
cells[id].id = id;
cells[id].name = data->dev_name;
cells[id].platform_data = data->pdata;
cells[id].data_size = data->pdata_size;
}
error = mfd_add_devices(dev, 0, cells, 2, NULL, 0);
if (error < 0) {
dev_err(dev, "cannot add mfd cells\n");
goto error_enable;
}
return 0;
error_enable:
free_irq(ssp->irq, ssp);
error_irq:
clk_put(ssp->clk);
error_clk:
iounmap(ssp->regs);
error_map:
release_mem_region(ssp->res->start, resource_size(ssp->res));
error_res:
kfree(ssp);
return error;
}
static int __devexit ti_ssp_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ti_ssp *ssp = dev_get_drvdata(dev);
mfd_remove_devices(dev);
clk_disable(ssp->clk);
free_irq(ssp->irq, ssp);
clk_put(ssp->clk);
iounmap(ssp->regs);
release_mem_region(ssp->res->start, resource_size(ssp->res));
kfree(ssp);
dev_set_drvdata(dev, NULL);
return 0;
}
static struct platform_driver ti_ssp_driver = {
.probe = ti_ssp_probe,
.remove = __devexit_p(ti_ssp_remove),
.driver = {
.name = "ti-ssp",
.owner = THIS_MODULE,
}
};
static int __init ti_ssp_init(void)
{
return platform_driver_register(&ti_ssp_driver);
}
module_init(ti_ssp_init);
static void __exit ti_ssp_exit(void)
{
platform_driver_unregister(&ti_ssp_driver);
}
module_exit(ti_ssp_exit);
MODULE_DESCRIPTION("Sequencer Serial Port (SSP) Driver");
MODULE_AUTHOR("Cyril Chemparathy");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ti-ssp");

10
drivers/spi/Kconfig
View File

@ -350,6 +350,16 @@ config SPI_TEGRA
help
SPI driver for NVidia Tegra SoCs
config SPI_TI_SSP
tristate "TI Sequencer Serial Port - SPI Support"
depends on MFD_TI_SSP
help
This selects an SPI master implementation using a TI sequencer
serial port.
To compile this driver as a module, choose M here: the
module will be called ti-ssp-spi.
config SPI_TOPCLIFF_PCH
tristate "Topcliff PCH SPI Controller"
depends on PCI

1
drivers/spi/Makefile
View File

@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o
obj-$(CONFIG_SPI_S3C64XX) += spi_s3c64xx.o
obj-$(CONFIG_SPI_TEGRA) += spi_tegra.o
obj-$(CONFIG_SPI_TI_SSP) += ti-ssp-spi.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi_topcliff_pch.o
obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o

402
drivers/spi/ti-ssp-spi.c Normal file
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@ -0,0 +1,402 @@
/*
* Sequencer Serial Port (SSP) based SPI master driver
*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/mfd/ti_ssp.h>
#define MODE_BITS (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH)
struct ti_ssp_spi {
struct spi_master *master;
struct device *dev;
spinlock_t lock;
struct list_head msg_queue;
struct completion complete;
bool shutdown;
struct workqueue_struct *workqueue;
struct work_struct work;
u8 mode, bpw;
int cs_active;
u32 pc_en, pc_dis, pc_wr, pc_rd;
void (*select)(int cs);
};
static u32 ti_ssp_spi_rx(struct ti_ssp_spi *hw)
{
u32 ret;
ti_ssp_run(hw->dev, hw->pc_rd, 0, &ret);
return ret;
}
static void ti_ssp_spi_tx(struct ti_ssp_spi *hw, u32 data)
{
ti_ssp_run(hw->dev, hw->pc_wr, data << (32 - hw->bpw), NULL);
}
static int ti_ssp_spi_txrx(struct ti_ssp_spi *hw, struct spi_message *msg,
struct spi_transfer *t)
{
int count;
if (hw->bpw <= 8) {
u8 *rx = t->rx_buf;
const u8 *tx = t->tx_buf;
for (count = 0; count < t->len; count += 1) {
if (t->tx_buf)
ti_ssp_spi_tx(hw, *tx++);
if (t->rx_buf)
*rx++ = ti_ssp_spi_rx(hw);
}
} else if (hw->bpw <= 16) {
u16 *rx = t->rx_buf;
const u16 *tx = t->tx_buf;
for (count = 0; count < t->len; count += 2) {
if (t->tx_buf)
ti_ssp_spi_tx(hw, *tx++);
if (t->rx_buf)
*rx++ = ti_ssp_spi_rx(hw);
}
} else {
u32 *rx = t->rx_buf;
const u32 *tx = t->tx_buf;
for (count = 0; count < t->len; count += 4) {
if (t->tx_buf)
ti_ssp_spi_tx(hw, *tx++);
if (t->rx_buf)
*rx++ = ti_ssp_spi_rx(hw);
}
}
msg->actual_length += count; /* bytes transferred */
dev_dbg(&msg->spi->dev, "xfer %s%s, %d bytes, %d bpw, count %d%s\n",
t->tx_buf ? "tx" : "", t->rx_buf ? "rx" : "", t->len,
hw->bpw, count, (count < t->len) ? " (under)" : "");
return (count < t->len) ? -EIO : 0; /* left over data */
}
static void ti_ssp_spi_chip_select(struct ti_ssp_spi *hw, int cs_active)
{
cs_active = !!cs_active;
if (cs_active == hw->cs_active)
return;
ti_ssp_run(hw->dev, cs_active ? hw->pc_en : hw->pc_dis, 0, NULL);
hw->cs_active = cs_active;
}
#define __SHIFT_OUT(bits) (SSP_OPCODE_SHIFT | SSP_OUT_MODE | \
cs_en | clk | SSP_COUNT((bits) * 2 - 1))
#define __SHIFT_IN(bits) (SSP_OPCODE_SHIFT | SSP_IN_MODE | \
cs_en | clk | SSP_COUNT((bits) * 2 - 1))
static int ti_ssp_spi_setup_transfer(struct ti_ssp_spi *hw, u8 bpw, u8 mode)
{
int error, idx = 0;
u32 seqram[16];
u32 cs_en, cs_dis, clk;
u32 topbits, botbits;
mode &= MODE_BITS;
if (mode == hw->mode && bpw == hw->bpw)
return 0;
cs_en = (mode & SPI_CS_HIGH) ? SSP_CS_HIGH : SSP_CS_LOW;
cs_dis = (mode & SPI_CS_HIGH) ? SSP_CS_LOW : SSP_CS_HIGH;
clk = (mode & SPI_CPOL) ? SSP_CLK_HIGH : SSP_CLK_LOW;
/* Construct instructions */
/* Disable Chip Select */
hw->pc_dis = idx;
seqram[idx++] = SSP_OPCODE_DIRECT | SSP_OUT_MODE | cs_dis | clk;
seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_dis | clk;
/* Enable Chip Select */
hw->pc_en = idx;
seqram[idx++] = SSP_OPCODE_DIRECT | SSP_OUT_MODE | cs_en | clk;
seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
/* Reads and writes need to be split for bpw > 16 */
topbits = (bpw > 16) ? 16 : bpw;
botbits = bpw - topbits;
/* Write */
hw->pc_wr = idx;
seqram[idx++] = __SHIFT_OUT(topbits) | SSP_ADDR_REG;
if (botbits)
seqram[idx++] = __SHIFT_OUT(botbits) | SSP_DATA_REG;
seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
/* Read */
hw->pc_rd = idx;
if (botbits)
seqram[idx++] = __SHIFT_IN(botbits) | SSP_ADDR_REG;
seqram[idx++] = __SHIFT_IN(topbits) | SSP_DATA_REG;
seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
error = ti_ssp_load(hw->dev, 0, seqram, idx);
if (error < 0)
return error;
error = ti_ssp_set_mode(hw->dev, ((mode & SPI_CPHA) ?
0 : SSP_EARLY_DIN));
if (error < 0)
return error;
hw->bpw = bpw;
hw->mode = mode;
return error;
}
static void ti_ssp_spi_work(struct work_struct *work)
{
struct ti_ssp_spi *hw = container_of(work, struct ti_ssp_spi, work);
spin_lock(&hw->lock);
while (!list_empty(&hw->msg_queue)) {
struct spi_message *m;
struct spi_device *spi;
struct spi_transfer *t = NULL;
int status = 0;
m = container_of(hw->msg_queue.next, struct spi_message,
queue);
list_del_init(&m->queue);
spin_unlock(&hw->lock);
spi = m->spi;
if (hw->select)
hw->select(spi->chip_select);
list_for_each_entry(t, &m->transfers, transfer_list) {
int bpw = spi->bits_per_word;
int xfer_status;
if (t->bits_per_word)
bpw = t->bits_per_word;
if (ti_ssp_spi_setup_transfer(hw, bpw, spi->mode) < 0)
break;
ti_ssp_spi_chip_select(hw, 1);
xfer_status = ti_ssp_spi_txrx(hw, m, t);
if (xfer_status < 0)
status = xfer_status;
if (t->delay_usecs)
udelay(t->delay_usecs);
if (t->cs_change)
ti_ssp_spi_chip_select(hw, 0);
}
ti_ssp_spi_chip_select(hw, 0);
m->status = status;
m->complete(m->context);
spin_lock(&hw->lock);
}
if (hw->shutdown)
complete(&hw->complete);
spin_unlock(&hw->lock);
}
static int ti_ssp_spi_setup(struct spi_device *spi)
{
if (spi->bits_per_word > 32)
return -EINVAL;
return 0;
}
static int ti_ssp_spi_transfer(struct spi_device *spi, struct spi_message *m)
{
struct ti_ssp_spi *hw;
struct spi_transfer *t;
int error = 0;
m->actual_length = 0;
m->status = -EINPROGRESS;
hw = spi_master_get_devdata(spi->master);
if (list_empty(&m->transfers) || !m->complete)
return -EINVAL;
list_for_each_entry(t, &m->transfers, transfer_list) {
if (t->len && !(t->rx_buf || t->tx_buf)) {
dev_err(&spi->dev, "invalid xfer, no buffer\n");
return -EINVAL;
}
if (t->len && t->rx_buf && t->tx_buf) {
dev_err(&spi->dev, "invalid xfer, full duplex\n");
return -EINVAL;
}
if (t->bits_per_word > 32) {
dev_err(&spi->dev, "invalid xfer width %d\n",
t->bits_per_word);
return -EINVAL;
}
}
spin_lock(&hw->lock);
if (hw->shutdown) {
error = -ESHUTDOWN;
goto error_unlock;
}
list_add_tail(&m->queue, &hw->msg_queue);
queue_work(hw->workqueue, &hw->work);
error_unlock:
spin_unlock(&hw->lock);
return error;
}
static int __devinit ti_ssp_spi_probe(struct platform_device *pdev)
{
const struct ti_ssp_spi_data *pdata;
struct ti_ssp_spi *hw;
struct spi_master *master;
struct device *dev = &pdev->dev;
int error = 0;
pdata = dev->platform_data;
if (!pdata) {
dev_err(dev, "platform data not found\n");
return -EINVAL;
}
master = spi_alloc_master(dev, sizeof(struct ti_ssp_spi));
if (!master) {
dev_err(dev, "cannot allocate SPI master\n");
return -ENOMEM;
}
hw = spi_master_get_devdata(master);
platform_set_drvdata(pdev, hw);
hw->master = master;
hw->dev = dev;
hw->select = pdata->select;
spin_lock_init(&hw->lock);
init_completion(&hw->complete);
INIT_LIST_HEAD(&hw->msg_queue);
INIT_WORK(&hw->work, ti_ssp_spi_work);
hw->workqueue = create_singlethread_workqueue(dev_name(dev));
if (!hw->workqueue) {
error = -ENOMEM;
dev_err(dev, "work queue creation failed\n");
goto error_wq;
}
error = ti_ssp_set_iosel(hw->dev, pdata->iosel);
if (error < 0) {
dev_err(dev, "io setup failed\n");
goto error_iosel;
}
master->bus_num = pdev->id;
master->num_chipselect = pdata->num_cs;
master->mode_bits = MODE_BITS;
master->flags = SPI_MASTER_HALF_DUPLEX;
master->setup = ti_ssp_spi_setup;
master->transfer = ti_ssp_spi_transfer;
error = spi_register_master(master);
if (error) {
dev_err(dev, "master registration failed\n");
goto error_reg;
}
return 0;
error_reg:
error_iosel:
destroy_workqueue(hw->workqueue);
error_wq:
spi_master_put(master);
return error;
}
static int __devexit ti_ssp_spi_remove(struct platform_device *pdev)
{
struct ti_ssp_spi *hw = platform_get_drvdata(pdev);
int error;
hw->shutdown = 1;
while (!list_empty(&hw->msg_queue)) {
error = wait_for_completion_interruptible(&hw->complete);
if (error < 0) {
hw->shutdown = 0;
return error;
}
}
destroy_workqueue(hw->workqueue);
spi_unregister_master(hw->master);
return 0;
}
static struct platform_driver ti_ssp_spi_driver = {
.probe = ti_ssp_spi_probe,
.remove = __devexit_p(ti_ssp_spi_remove),
.driver = {
.name = "ti-ssp-spi",
.owner = THIS_MODULE,
},
};
static int __init ti_ssp_spi_init(void)
{
return platform_driver_register(&ti_ssp_spi_driver);
}
module_init(ti_ssp_spi_init);
static void __exit ti_ssp_spi_exit(void)
{
platform_driver_unregister(&ti_ssp_spi_driver);
}
module_exit(ti_ssp_spi_exit);
MODULE_DESCRIPTION("SSP SPI Master");
MODULE_AUTHOR("Cyril Chemparathy");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ti-ssp-spi");

93
include/linux/mfd/ti_ssp.h Normal file
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@ -0,0 +1,93 @@
/*
* Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __TI_SSP_H__
#define __TI_SSP_H__
struct ti_ssp_dev_data {
const char *dev_name;
void *pdata;
size_t pdata_size;
};
struct ti_ssp_data {
unsigned long out_clock;
struct ti_ssp_dev_data dev_data[2];
};
struct ti_ssp_spi_data {
unsigned long iosel;
int num_cs;
void (*select)(int cs);
};
/*
* Sequencer port IO pin configuration bits. These do not correlate 1-1 with
* the hardware. The iosel field in the port data combines iosel1 and iosel2,
* and is therefore not a direct map to register space. It is best to use the
* macros below to construct iosel values.
*
* least significant 16 bits --> iosel1
* most significant 16 bits --> iosel2
*/
#define SSP_IN 0x0000
#define SSP_DATA 0x0001
#define SSP_CLOCK 0x0002
#define SSP_CHIPSEL 0x0003
#define SSP_OUT 0x0004
#define SSP_PIN_SEL(pin, v) ((v) << ((pin) * 3))
#define SSP_PIN_MASK(pin) SSP_PIN_SEL(pin, 0x7)
#define SSP_INPUT_SEL(pin) ((pin) << 16)
/* Sequencer port config bits */
#define SSP_EARLY_DIN BIT(8)
#define SSP_DELAY_DOUT BIT(9)
/* Sequence map definitions */
#define SSP_CLK_HIGH BIT(0)
#define SSP_CLK_LOW 0
#define SSP_DATA_HIGH BIT(1)
#define SSP_DATA_LOW 0
#define SSP_CS_HIGH BIT(2)
#define SSP_CS_LOW 0
#define SSP_OUT_MODE BIT(3)
#define SSP_IN_MODE 0
#define SSP_DATA_REG BIT(4)
#define SSP_ADDR_REG 0
#define SSP_OPCODE_DIRECT ((0x0) << 5)
#define SSP_OPCODE_TOGGLE ((0x1) << 5)
#define SSP_OPCODE_SHIFT ((0x2) << 5)
#define SSP_OPCODE_BRANCH0 ((0x4) << 5)
#define SSP_OPCODE_BRANCH1 ((0x5) << 5)
#define SSP_OPCODE_BRANCH ((0x6) << 5)
#define SSP_OPCODE_STOP ((0x7) << 5)
#define SSP_BRANCH(addr) ((addr) << 8)
#define SSP_COUNT(cycles) ((cycles) << 8)
int ti_ssp_raw_read(struct device *dev);
int ti_ssp_raw_write(struct device *dev, u32 val);
int ti_ssp_load(struct device *dev, int offs, u32* prog, int len);
int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output);
int ti_ssp_set_mode(struct device *dev, int mode);
int ti_ssp_set_iosel(struct device *dev, u32 iosel);
#endif /* __TI_SSP_H__ */