forked from Minki/linux
arm64: dts: renesas: Initial r8a774b1 SoC device tree
Basic support for the RZ/G2N (R8A774B1) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569589584-56917-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
Geert Uytterhoeven
parent
652fd0f44e
commit
9b33e3001b
472
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
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472
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
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@ -0,0 +1,472 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a774b1 SoC
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
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#include <dt-bindings/power/r8a774b1-sysc.h>
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/ {
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compatible = "renesas,r8a774b1";
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#address-cells = <2>;
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#size-cells = <2>;
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency
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* clocks by default.
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* Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc R8A774B1_PD_CA57_CPU0>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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#cooling-cells = <2>;
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dynamic-power-coefficient = <854>;
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clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
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};
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a57_1: cpu@1 {
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compatible = "arm,cortex-a57";
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reg = <0x1>;
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device_type = "cpu";
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power-domains = <&sysc R8A774B1_PD_CA57_CPU1>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
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};
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L2_CA57: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc R8A774B1_PD_CA57_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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/* External PCIe clock - can be overridden by the board */
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pcie_bus_clk: pcie_bus {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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pmu_a57 {
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compatible = "arm,cortex-a57-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a57_0>, <&a57_1>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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reg = <0 0xe6020000 0 0x0c>;
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/* placeholder */
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};
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gpio0: gpio@e6050000 {
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reg = <0 0xe6050000 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio1: gpio@e6051000 {
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reg = <0 0xe6051000 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio2: gpio@e6052000 {
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reg = <0 0xe6052000 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio3: gpio@e6053000 {
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reg = <0 0xe6053000 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio4: gpio@e6054000 {
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reg = <0 0xe6054000 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio5: gpio@e6055000 {
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reg = <0 0xe6055000 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio6: gpio@e6055400 {
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reg = <0 0xe6055400 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio7: gpio@e6055800 {
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reg = <0 0xe6055800 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a774b1";
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reg = <0 0xe6060000 0 0x50c>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a774b1-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a774b1-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a774b1-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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i2c4: i2c@e66d8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0xe66d8000 0 0x40>;
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/* placeholder */
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};
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hscif0: serial@e6540000 {
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reg = <0 0xe6540000 0 0x60>;
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/* placeholder */
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};
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hsusb: usb@e6590000 {
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reg = <0 0xe6590000 0 0x200>;
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/* placeholder */
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};
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usb3_phy0: usb-phy@e65ee000 {
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reg = <0 0xe65ee000 0 0x90>;
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#phy-cells = <0>;
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/* placeholder */
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};
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avb: ethernet@e6800000 {
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reg = <0 0xe6800000 0 0x800>;
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/* placeholder */
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};
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can0: can@e6c30000 {
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reg = <0 0xe6c30000 0 0x1000>;
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/* placeholder */
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};
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can1: can@e6c38000 {
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reg = <0 0xe6c38000 0 0x1000>;
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/* placeholder */
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};
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canfd: can@e66c0000 {
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reg = <0 0xe66c0000 0 0x8000>;
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/* placeholder */
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a774b1",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>,
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<&cpg CPG_CORE R8A774B1_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 310>;
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status = "disabled";
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};
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rcar_sound: sound@ec500000 {
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reg = <0 0xec500000 0 0x1000>, /* SCU */
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<0 0xec5a0000 0 0x100>, /* ADG */
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<0 0xec540000 0 0x1000>, /* SSIU */
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<0 0xec541000 0 0x280>, /* SSI */
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<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
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rcar_sound,ssi {
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ssi0: ssi-0 { };
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ssi1: ssi-1 { };
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ssi2: ssi-2 { };
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ssi3: ssi-3 { };
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ssi4: ssi-4 { };
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ssi5: ssi-5 { };
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ssi6: ssi-6 { };
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ssi7: ssi-7 { };
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ssi8: ssi-8 { };
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ssi9: ssi-9 { };
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};
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};
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xhci0: usb@ee000000 {
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reg = <0 0xee000000 0 0xc00>;
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/* placeholder */
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};
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usb3_peri0: usb@ee020000 {
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reg = <0 0xee020000 0 0x400>;
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/* placeholder */
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};
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ohci0: usb@ee080000 {
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reg = <0 0xee080000 0 0x100>;
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/* placeholder */
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};
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ohci1: usb@ee0a0000 {
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reg = <0 0xee0a0000 0 0x100>;
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/* placeholder */
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};
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ehci0: usb@ee080100 {
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reg = <0 0xee080100 0 0x100>;
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/* placeholder */
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};
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ehci1: usb@ee0a0100 {
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reg = <0 0xee0a0100 0 0x100>;
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/* placeholder */
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};
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usb2_phy0: usb-phy@ee080200 {
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reg = <0 0xee080200 0 0x700>;
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/* placeholder */
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};
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usb2_phy1: usb-phy@ee0a0200 {
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reg = <0 0xee0a0200 0 0x700>;
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/* placeholder */
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};
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sdhi0: sd@ee100000 {
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reg = <0 0xee100000 0 0x2000>;
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/* placeholder */
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};
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sdhi1: sd@ee120000 {
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reg = <0 0xee120000 0 0x2000>;
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/* placeholder */
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};
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sdhi2: sd@ee140000 {
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reg = <0 0xee140000 0 0x2000>;
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/* placeholder */
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};
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sdhi3: sd@ee160000 {
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reg = <0 0xee160000 0 0x2000>;
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/* placeholder */
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};
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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pciec0: pcie@fe000000 {
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reg = <0 0xfe000000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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/* placeholder */
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};
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pciec1: pcie@ee800000 {
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reg = <0 0xee800000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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/* placeholder */
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};
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hdmi0: hdmi@fead0000 {
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reg = <0 0xfead0000 0 0x10000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dw_hdmi0_in: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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};
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};
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};
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du: display@feb00000 {
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reg = <0 0xfeb00000 0 0x80000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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du_out_rgb: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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du_out_hdmi0: endpoint {
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};
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};
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port@2 {
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reg = <2>;
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du_out_lvds0: endpoint {
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};
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};
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};
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/* External USB clocks - can be overridden by the board */
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usb3s0_clk: usb3s0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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usb_extal_clk: usb_extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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