forked from Minki/linux
ARM: 8606/1: V7M: introduce cache operations
This commit implements the cache operation for V7M. It is based on V7 counterpart and differs as follows: - cache operations are memory mapped - only Thumb instruction set is supported - we don't handle user access faults Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Joachim Eastwood <manabian@gmail.com> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Vladimir Murzin
Russell King
parent
b2bf482a50
commit
9a1af5f220
453
arch/arm/mm/cache-v7m.S
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453
arch/arm/mm/cache-v7m.S
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@ -0,0 +1,453 @@
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/*
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* linux/arch/arm/mm/cache-v7m.S
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*
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* Based on linux/arch/arm/mm/cache-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2005 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7M processor support.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/errno.h>
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#include <asm/unwind.h>
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#include <asm/v7m.h>
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#include "proc-macros.S"
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/* Generic V7M read/write macros for memory mapped cache operations */
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.macro v7m_cache_read, rt, reg
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movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
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movt \rt, #:upper16:BASEADDR_V7M_SCB + \reg
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ldr \rt, [\rt]
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.endm
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.macro v7m_cacheop, rt, tmp, op, c = al
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movw\c \tmp, #:lower16:BASEADDR_V7M_SCB + \op
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movt\c \tmp, #:upper16:BASEADDR_V7M_SCB + \op
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str\c \rt, [\tmp]
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.endm
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.macro read_ccsidr, rt
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v7m_cache_read \rt, V7M_SCB_CCSIDR
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.endm
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.macro read_clidr, rt
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v7m_cache_read \rt, V7M_SCB_CLIDR
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.endm
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.macro write_csselr, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
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.endm
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/*
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* dcisw: Invalidate data cache by set/way
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*/
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.macro dcisw, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
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.endm
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/*
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* dccisw: Clean and invalidate data cache by set/way
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*/
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.macro dccisw, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
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.endm
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/*
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* dccimvac: Clean and invalidate data cache line by MVA to PoC.
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*/
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.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
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.macro dccimvac\c, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
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.endm
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.endr
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/*
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* dcimvac: Invalidate data cache line by MVA to PoC
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*/
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.macro dcimvac, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC
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.endm
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/*
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* dccmvau: Clean data cache line by MVA to PoU
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*/
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.macro dccmvau, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAU
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.endm
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/*
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* dccmvac: Clean data cache line by MVA to PoC
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*/
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.macro dccmvac, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAC
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.endm
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/*
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* icimvau: Invalidate instruction caches by MVA to PoU
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*/
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.macro icimvau, rt, tmp
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v7m_cacheop \rt, \tmp, V7M_SCB_ICIMVAU
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.endm
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/*
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* Invalidate the icache, inner shareable if SMP, invalidate BTB for UP.
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* rt data ignored by ICIALLU(IS), so can be used for the address
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*/
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.macro invalidate_icache, rt
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v7m_cacheop \rt, \rt, V7M_SCB_ICIALLU
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mov \rt, #0
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.endm
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/*
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* Invalidate the BTB, inner shareable if SMP.
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* rt data ignored by BPIALL, so it can be used for the address
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*/
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.macro invalidate_bp, rt
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v7m_cacheop \rt, \rt, V7M_SCB_BPIALL
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mov \rt, #0
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.endm
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ENTRY(v7m_invalidate_l1)
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mov r0, #0
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write_csselr r0, r1
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read_ccsidr r0
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movw r1, #0x7fff
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and r2, r1, r0, lsr #13
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movw r1, #0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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dcisw r5, r6
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb st
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isb
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ret lr
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ENDPROC(v7m_invalidate_l1)
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/*
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* v7m_flush_icache_all()
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*
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* Flush the whole I-cache.
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*
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* Registers:
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* r0 - set to 0
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*/
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ENTRY(v7m_flush_icache_all)
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invalidate_icache r0
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ret lr
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ENDPROC(v7m_flush_icache_all)
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/*
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* v7m_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11
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*/
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ENTRY(v7m_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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read_clidr r0
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq finished @ if loc is 0, then no need to clean
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start_flush_levels:
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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#ifdef CONFIG_PREEMPT
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save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
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#endif
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write_csselr r10, r1 @ set current cache level
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isb @ isb to sych the new cssr&csidr
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read_ccsidr r1 @ read the new csidr
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#ifdef CONFIG_PREEMPT
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restore_irqs_notrace r9
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#endif
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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mov r9, r7 @ create working copy of max index
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loop2:
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lsl r6, r4, r5
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orr r11, r10, r6 @ factor way and cache number into r11
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lsl r6, r9, r2
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orr r11, r11, r6 @ factor index number into r11
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dccisw r11, r6 @ clean/invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, #1 @ decrement the way
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bge loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt flush_levels
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finished:
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mov r10, #0 @ swith back to cache level 0
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write_csselr r10, r3 @ select current cache level in cssr
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dsb st
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isb
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ret lr
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ENDPROC(v7m_flush_dcache_all)
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/*
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* v7m_flush_cache_all()
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*
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* Flush the entire cache system.
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* The data cache flush is now achieved using atomic clean / invalidates
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* working outwards from L1 cache. This is done using Set/Way based cache
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* maintenance instructions.
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* The instruction cache can still be invalidated back to the point of
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* unification in a single instruction.
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*
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*/
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ENTRY(v7m_flush_kern_cache_all)
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stmfd sp!, {r4-r7, r9-r11, lr}
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bl v7m_flush_dcache_all
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invalidate_icache r0
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ldmfd sp!, {r4-r7, r9-r11, lr}
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ret lr
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ENDPROC(v7m_flush_kern_cache_all)
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/*
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* v7m_flush_cache_all()
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*
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* Flush all TLB entries in a particular address space
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v7m_flush_user_cache_all)
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/*FALLTHROUGH*/
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/*
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* v7m_flush_cache_range(start, end, flags)
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*
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* Flush a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vm_area_struct flags describing address space
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*
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* It is assumed that:
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* - we have a VIPT cache.
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*/
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ENTRY(v7m_flush_user_cache_range)
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ret lr
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ENDPROC(v7m_flush_user_cache_all)
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ENDPROC(v7m_flush_user_cache_range)
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/*
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* v7m_coherent_kern_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v7m_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* v7m_coherent_user_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v7m_coherent_user_range)
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UNWIND(.fnstart )
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r12, r0, r3
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1:
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/*
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* We use open coded version of dccmvau otherwise USER() would
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* point at movw instruction.
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*/
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dccmvau r12, r3
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add r12, r12, r2
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cmp r12, r1
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blo 1b
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dsb ishst
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icache_line_size r2, r3
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sub r3, r2, #1
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bic r12, r0, r3
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2:
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icimvau r12, r3
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add r12, r12, r2
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cmp r12, r1
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blo 2b
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invalidate_bp r0
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dsb ishst
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isb
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ret lr
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UNWIND(.fnend )
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ENDPROC(v7m_coherent_kern_range)
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ENDPROC(v7m_coherent_user_range)
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/*
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* v7m_flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure that the data held in the page kaddr is written back
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* to the page in question.
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(v7m_flush_kern_dcache_area)
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dcache_line_size r2, r3
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add r1, r0, r1
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sub r3, r2, #1
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bic r0, r0, r3
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1:
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dccimvac r0, r3 @ clean & invalidate D line / unified line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7m_flush_kern_dcache_area)
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/*
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* v7m_dma_inv_range(start,end)
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*
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* Invalidate the data cache within the specified region; we will
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* be performing a DMA operation in this region and we want to
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* purge old data in the cache.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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v7m_dma_inv_range:
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dcache_line_size r2, r3
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sub r3, r2, #1
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tst r0, r3
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bic r0, r0, r3
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dccimvacne r0, r3
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subne r3, r2, #1 @ restore r3, corrupted by v7m's dccimvac
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tst r1, r3
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bic r1, r1, r3
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dccimvacne r1, r3
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1:
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dcimvac r0, r3
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7m_dma_inv_range)
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/*
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* v7m_dma_clean_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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v7m_dma_clean_range:
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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1:
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dccmvac r0, r3 @ clean D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7m_dma_clean_range)
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/*
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* v7m_dma_flush_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v7m_dma_flush_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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1:
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dccimvac r0, r3 @ clean & invalidate D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb st
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ret lr
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ENDPROC(v7m_dma_flush_range)
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v7m_dma_map_area)
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add r1, r1, r0
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teq r2, #DMA_FROM_DEVICE
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beq v7m_dma_inv_range
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b v7m_dma_clean_range
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ENDPROC(v7m_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v7m_dma_unmap_area)
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add r1, r1, r0
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teq r2, #DMA_TO_DEVICE
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bne v7m_dma_inv_range
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ret lr
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ENDPROC(v7m_dma_unmap_area)
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.globl v7m_flush_kern_cache_louis
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.equ v7m_flush_kern_cache_louis, v7m_flush_kern_cache_all
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions v7m
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@ -7,6 +7,10 @@
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#ifdef CONFIG_CPU_V7M
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#include <asm/v7m.h>
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#endif
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/*
|
||||
* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
|
||||
*/
|
||||
@ -70,7 +74,13 @@
|
||||
* on ARMv7.
|
||||
*/
|
||||
.macro dcache_line_size, reg, tmp
|
||||
#ifdef CONFIG_CPU_V7M
|
||||
movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
|
||||
movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
|
||||
ldr \tmp, [\tmp]
|
||||
#else
|
||||
mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
|
||||
#endif
|
||||
lsr \tmp, \tmp, #16
|
||||
and \tmp, \tmp, #0xf @ cache line size encoding
|
||||
mov \reg, #4 @ bytes per word
|
||||
@ -82,7 +92,13 @@
|
||||
* on ARMv7.
|
||||
*/
|
||||
.macro icache_line_size, reg, tmp
|
||||
#ifdef CONFIG_CPU_V7M
|
||||
movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
|
||||
movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
|
||||
ldr \tmp, [\tmp]
|
||||
#else
|
||||
mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
|
||||
#endif
|
||||
and \tmp, \tmp, #0xf @ cache line size encoding
|
||||
mov \reg, #4 @ bytes per word
|
||||
mov \reg, \reg, lsl \tmp @ actual cache line size
|
||||
|
||||
Loading…
Reference in New Issue
Block a user