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drm/nouveau/gr: disable fifo access and idle before suspend ctx unload

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2011-07-20 11:44:52 +10:00
parent 6c320fef58
commit 9962cc6eba
4 changed files with 20 additions and 0 deletions
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5
drivers/gpu/drm/nouveau/nv04_graph.c
View File

@ -540,6 +540,11 @@ nv04_graph_init(struct drm_device *dev, int engine)
static int static int
nv04_graph_fini(struct drm_device *dev, int engine, bool suspend) nv04_graph_fini(struct drm_device *dev, int engine, bool suspend)
{ {
nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) {
nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
return -EBUSY;
}
nv04_graph_unload_context(dev); nv04_graph_unload_context(dev);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000); nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
return 0; return 0;

5
drivers/gpu/drm/nouveau/nv10_graph.c
View File

@ -959,6 +959,11 @@ nv10_graph_init(struct drm_device *dev, int engine)
static int static int
nv10_graph_fini(struct drm_device *dev, int engine, bool suspend) nv10_graph_fini(struct drm_device *dev, int engine, bool suspend)
{ {
nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) {
nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
return -EBUSY;
}
nv10_graph_unload_context(dev); nv10_graph_unload_context(dev);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000); nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
return 0; return 0;

5
drivers/gpu/drm/nouveau/nv20_graph.c
View File

@ -656,6 +656,11 @@ nv30_graph_init(struct drm_device *dev, int engine)
int int
nv20_graph_fini(struct drm_device *dev, int engine, bool suspend) nv20_graph_fini(struct drm_device *dev, int engine, bool suspend)
{ {
nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) {
nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
return -EBUSY;
}
nv20_graph_unload_context(dev); nv20_graph_unload_context(dev);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000); nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
return 0; return 0;

5
drivers/gpu/drm/nouveau/nv50_graph.c
View File

@ -256,6 +256,11 @@ nv50_graph_init(struct drm_device *dev, int engine)
static int static int
nv50_graph_fini(struct drm_device *dev, int engine, bool suspend) nv50_graph_fini(struct drm_device *dev, int engine, bool suspend)
{ {
nv_mask(dev, 0x400500, 0x00010001, 0x00000000);
if (!nv_wait(dev, 0x400700, ~0, 0) && suspend) {
nv_mask(dev, 0x400500, 0x00010001, 0x00010001);
return -EBUSY;
}
nv50_graph_unload_context(dev); nv50_graph_unload_context(dev);
nv_wr32(dev, 0x40013c, 0x00000000); nv_wr32(dev, 0x40013c, 0x00000000);
return 0; return 0;