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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Browse Source 
Pull m68knommu updates from Greg Ungerer:
 "The bulk of the changes are generalizing the ColdFire v3 core support
  and adding in 537x CPU support.  Also a couple of other bug fixes, one
  to fix a reintroduction of a past bug in the romfs filesystem nommu
  support."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: enable Timer on coldfire 532x
  m68knommu: fix ColdFire 5373/5329 QSPI base address
  m68knommu: add support for configuring a Freescale M5373EVB board
  m68knommu: add support for the ColdFire 537x family of CPUs
  m68knommu: make ColdFire M532x platform support more v3 generic
  m68knommu: create and use a common M53xx ColdFire class of CPUs
  m68k: remove unused asm/dbg.h
  m68k: Set ColdFire ACR1 cache mode depending on kernel configuration
  romfs: fix nommu map length to keep inside filesystem
  m68k: clean up unused "config ROMVECSIZE"
This commit is contained in:
Linus Torvalds 2013-05-10 07:22:35 -07:00
commit 977b58e1dd
16 changed files with 60 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/m68k/Kconfig.cpu
View File

@ -223,13 +223,25 @@ config M5307
help
Motorola ColdFire 5307 processor support.
config M53xx
bool
config M532x
bool "MCF532x"
depends on !MMU
select M53xx
select HAVE_CACHE_CB
help
Freescale (Motorola) ColdFire 532x processor support.
config M537x
bool "MCF537x"
depends on !MMU
select M53xx
select HAVE_CACHE_CB
help
Freescale ColdFire 537x processor support.
config M5407
bool "MCF5407"
depends on !MMU

16
arch/m68k/Kconfig.machine
View File

@ -358,6 +358,13 @@ config COBRA5329
help
Support for the senTec COBRA5329 board.
config M5373EVB
bool "Freescale M5373EVB board support"
depends on M537x
select FREESCALE
help
Support for the Freescale M5373EVB board.
config M5407C3
bool "Motorola M5407C3 board support"
depends on M5407
@ -539,15 +546,6 @@ config ROMVEC
68000 type variants the vectors are at the base of the boot device
on system startup.
config ROMVECSIZE
hex "Size of ROM vector region (in bytes)"
default "0x400"
depends on ROM
help
Define the size of the vector region in ROM. For most 68000
variants this would be 0x400 bytes in size. Set to 0 if you do
not want a vector region at the start of the ROM.
config ROMSTART
hex "Address of the base of system image in ROM"
default "0x400"

1
arch/m68k/Makefile
View File

@ -45,6 +45,7 @@ cpuflags-$(CONFIG_M5441x) := $(call cc-option,-mcpu=54455,-mcfv4e)
cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
cpuflags-$(CONFIG_M537x) := $(call cc-option,-mcpu=537x,-m5307)
cpuflags-$(CONFIG_M5307) := $(call cc-option,-mcpu=5307,-m5200)
cpuflags-$(CONFIG_M528x) := $(call cc-option,-mcpu=528x,-m5307)
cpuflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)

6
arch/m68k/include/asm/dbg.h
View File

@ -1,6 +0,0 @@
#define DEBUG 1
#ifdef CONFIG_COLDFIRE
#define BREAK asm volatile ("halt")
#else
#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0
#endif

2
arch/m68k/include/asm/dma.h
View File

@ -39,7 +39,7 @@
#define MAX_M68K_DMA_CHANNELS 4
#elif defined(CONFIG_M5272)
#define MAX_M68K_DMA_CHANNELS 1
#elif defined(CONFIG_M532x)
#elif defined(CONFIG_M53xx)
#define MAX_M68K_DMA_CHANNELS 0
#else
#define MAX_M68K_DMA_CHANNELS 2

4
arch/m68k/include/asm/m53xxacr.h
View File

@ -55,8 +55,8 @@
#define CACHE_SIZE 0x2000 /* 8k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#elif defined(CONFIG_M532x)
#define CACHE_SIZE 0x4000 /* 32k of unified cache */
#elif defined(CONFIG_M53xx)
#define CACHE_SIZE 0x4000 /* 16k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#endif

12
arch/m68k/include/asm/m532xsim.h → arch/m68k/include/asm/m53xxsim.h
View File

@ -1,15 +1,15 @@
/****************************************************************************/
/*
* m532xsim.h -- ColdFire 5329 registers
* m53xxsim.h -- ColdFire 5329 registers
*/
/****************************************************************************/
#ifndef m532xsim_h
#define m532xsim_h
#ifndef m53xxsim_h
#define m53xxsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m532x)"
#define CPU_NAME "COLDFIRE(m53xx)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 3)
@ -107,7 +107,7 @@
/*
* QSPI module.
*/
#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
#define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */
#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
#define MCFQSPI_CS0 84
@ -1238,4 +1238,4 @@
#define MCFEPORT_EPFR (0xFC094006)
/********************************************************************/
#endif /* m532xsim_h */
#endif /* m53xxsim_h */

7
arch/m68k/include/asm/m54xxacr.h
View File

@ -96,8 +96,13 @@
*/
#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
#if defined(CONFIG_CACHE_COPYBACK)
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP)
ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
#else
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
#endif
#define ACR2_MODE 0
#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP)

10
arch/m68k/include/asm/mcfgpio.h
View File

@ -104,7 +104,7 @@ static inline void gpio_free(unsigned gpio)
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
defined(CONFIG_M5441x)
/* These parts have GPIO organized by 8 bit ports */
@ -139,7 +139,7 @@ static inline void gpio_free(unsigned gpio)
#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
/*
* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
* read-modify-write to change an output and a GPIO module which has separate
@ -195,7 +195,7 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
return MCFSIM2_GPIO1READ;
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#if !defined(CONFIG_M5441x)
if (gpio < 8)
return MCFEPORT_EPPDR;
@ -237,7 +237,7 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
return MCFSIM2_GPIO1WRITE;
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#if !defined(CONFIG_M5441x)
if (gpio < 8)
return MCFEPORT_EPDR;
@ -279,7 +279,7 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
return MCFSIM2_GPIO1ENABLE;
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#if !defined(CONFIG_M5441x)
if (gpio < 8)
return MCFEPORT_EPDDR;

4
arch/m68k/include/asm/mcfsim.h
View File

@ -36,8 +36,8 @@
#elif defined(CONFIG_M5307)
#include <asm/m5307sim.h>
#include <asm/mcfintc.h>
#elif defined(CONFIG_M532x)
#include <asm/m532xsim.h>
#elif defined(CONFIG_M53xx)
#include <asm/m53xxsim.h>
#elif defined(CONFIG_M5407)
#include <asm/m5407sim.h>
#include <asm/mcfintc.h>

2
arch/m68k/include/asm/mcftimer.h
View File

@ -19,7 +19,7 @@
#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
#else
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */

2
arch/m68k/platform/coldfire/Makefile
View File

@ -25,7 +25,7 @@ obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o
obj-$(CONFIG_M53xx) += m53xx.o timers.o intc-simr.o reset.o
obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o

23
arch/m68k/platform/coldfire/m532x.c → arch/m68k/platform/coldfire/m53xx.c
View File

@ -1,7 +1,7 @@
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/532x/config.c
* m53xx.c -- platform support for ColdFire 53xx based boards
*
* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
* Copyright (C) 2000, Lineo (www.lineo.com)
@ -118,7 +118,8 @@ static struct clk * const enable_clks[] __initconst = {
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
&__clk_0_26, /* mcfuart.2 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_32, /* mcfpit.0 */
&__clk_0_33, /* mcfpit.1 */
&__clk_0_37, /* mcfeport.0 */
@ -134,8 +135,6 @@ static struct clk * const disable_clks[] __initconst = {
&__clk_0_17, /* edma */
&__clk_0_22, /* mcfi2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
&__clk_0_34, /* mcfpit.2 */
@ -153,7 +152,7 @@ static struct clk * const disable_clks[] __initconst = {
};
static void __init m532x_clk_init(void)
static void __init m53xx_clk_init(void)
{
unsigned i;
@ -169,7 +168,7 @@ static void __init m532x_clk_init(void)
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
static void __init m532x_qspi_init(void)
static void __init m53xx_qspi_init(void)
{
/* setup QSPS pins for QSPI with gpio CS control */
writew(0x01f0, MCFGPIO_PAR_QSPI);
@ -179,7 +178,7 @@ static void __init m532x_qspi_init(void)
/***************************************************************************/
static void __init m532x_uarts_init(void)
static void __init m53xx_uarts_init(void)
{
/* UART GPIO initialization */
writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
@ -187,7 +186,7 @@ static void __init m532x_uarts_init(void)
/***************************************************************************/
static void __init m532x_fec_init(void)
static void __init m53xx_fec_init(void)
{
u8 v;
@ -217,11 +216,11 @@ void __init config_BSP(char *commandp, int size)
}
#endif
mach_sched_init = hw_timer_init;
m532x_clk_init();
m532x_uarts_init();
m532x_fec_init();
m53xx_clk_init();
m53xx_uarts_init();
m53xx_fec_init();
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
m532x_qspi_init();
m53xx_qspi_init();
#endif
#ifdef CONFIG_BDM_DISABLE

2
arch/m68k/platform/coldfire/timers.c
View File

@ -36,7 +36,7 @@
*/
void coldfire_profile_init(void);
#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#define __raw_readtrr __raw_readl
#define __raw_writetrr __raw_writel
#else

1
drivers/tty/serial/68328serial.c
View File

@ -14,7 +14,6 @@
* 2.4/2.5 port David McCullough
*/
#include <asm/dbg.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/serial.h>

5
fs/romfs/mmap-nommu.c
View File

@ -49,8 +49,11 @@ static unsigned long romfs_get_unmapped_area(struct file *file,
return (unsigned long) -EINVAL;
offset += ROMFS_I(inode)->i_dataoffset;
if (offset > mtd->size - len)
if (offset >= mtd->size)
return (unsigned long) -EINVAL;
/* the mapping mustn't extend beyond the EOF */
if ((offset + len) > mtd->size)
len = mtd->size - offset;
ret = mtd_get_unmapped_area(mtd, len, offset, flags);
if (ret == -EOPNOTSUPP)