forked from Minki/linux
Merge branch 'stmmac-fixes'
Joakim Zhang says: ==================== patches for stmmac A patch set for stmmac, fix some driver issues. ChangeLogs: V1->V2: * add Fixes tag. * add patch 5/5 into this patch set. V2->V3: * rebase to latest net tree where fixes go. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
9756bb63e8
@ -246,13 +246,7 @@ static int imx_dwmac_probe(struct platform_device *pdev)
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goto err_parse_dt;
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}
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ret = dma_set_mask_and_coherent(&pdev->dev,
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DMA_BIT_MASK(dwmac->ops->addr_width));
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if (ret) {
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dev_err(&pdev->dev, "DMA mask set failed\n");
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goto err_dma_mask;
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}
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plat_dat->addr64 = dwmac->ops->addr_width;
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plat_dat->init = imx_dwmac_init;
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plat_dat->exit = imx_dwmac_exit;
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plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
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@ -272,7 +266,6 @@ static int imx_dwmac_probe(struct platform_device *pdev)
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err_dwmac_init:
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err_drv_probe:
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imx_dwmac_exit(pdev, plat_dat->bsp_priv);
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err_dma_mask:
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err_parse_dt:
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err_match_data:
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stmmac_remove_config_dt(pdev, plat_dat);
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@ -22,7 +22,7 @@ int dwmac4_dma_reset(void __iomem *ioaddr)
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return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
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!(value & DMA_BUS_MODE_SFT_RESET),
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10000, 100000);
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10000, 1000000);
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}
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void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)
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@ -1533,6 +1533,19 @@ static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
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stmmac_free_tx_buffer(priv, queue, i);
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}
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/**
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* stmmac_free_tx_skbufs - free TX skb buffers
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* @priv: private structure
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*/
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static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
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{
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u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
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u32 queue;
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for (queue = 0; queue < tx_queue_cnt; queue++)
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dma_free_tx_skbufs(priv, queue);
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}
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/**
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* free_dma_rx_desc_resources - free RX dma desc resources
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* @priv: private structure
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@ -2895,9 +2908,6 @@ static int stmmac_release(struct net_device *dev)
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struct stmmac_priv *priv = netdev_priv(dev);
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u32 chan;
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if (priv->eee_enabled)
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del_timer_sync(&priv->eee_ctrl_timer);
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if (device_may_wakeup(priv->device))
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phylink_speed_down(priv->phylink, false);
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/* Stop and disconnect the PHY */
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@ -2916,6 +2926,11 @@ static int stmmac_release(struct net_device *dev)
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if (priv->lpi_irq > 0)
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free_irq(priv->lpi_irq, dev);
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if (priv->eee_enabled) {
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priv->tx_path_in_lpi_mode = false;
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del_timer_sync(&priv->eee_ctrl_timer);
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}
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/* Stop TX/RX DMA and clear the descriptors */
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stmmac_stop_all_dma(priv);
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@ -4930,6 +4945,14 @@ int stmmac_dvr_probe(struct device *device,
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dev_info(priv->device, "SPH feature enabled\n");
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}
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/* The current IP register MAC_HW_Feature1[ADDR64] only define
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* 32/40/64 bit width, but some SOC support others like i.MX8MP
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* support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
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* So overwrite dma_cap.addr64 according to HW real design.
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*/
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if (priv->plat->addr64)
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priv->dma_cap.addr64 = priv->plat->addr64;
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if (priv->dma_cap.addr64) {
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ret = dma_set_mask_and_coherent(device,
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DMA_BIT_MASK(priv->dma_cap.addr64));
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@ -5142,6 +5165,11 @@ int stmmac_suspend(struct device *dev)
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for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
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del_timer_sync(&priv->tx_queue[chan].txtimer);
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if (priv->eee_enabled) {
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priv->tx_path_in_lpi_mode = false;
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del_timer_sync(&priv->eee_ctrl_timer);
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}
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/* Stop TX/RX DMA */
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stmmac_stop_all_dma(priv);
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@ -5247,11 +5275,20 @@ int stmmac_resume(struct device *dev)
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return ret;
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}
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if (!device_may_wakeup(priv->device) || !priv->plat->pmt) {
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rtnl_lock();
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phylink_start(priv->phylink);
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/* We may have called phylink_speed_down before */
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phylink_speed_up(priv->phylink);
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rtnl_unlock();
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}
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rtnl_lock();
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mutex_lock(&priv->lock);
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stmmac_reset_queues_param(priv);
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stmmac_free_tx_skbufs(priv);
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stmmac_clear_descriptors(priv);
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stmmac_hw_setup(ndev, false);
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@ -5265,14 +5302,6 @@ int stmmac_resume(struct device *dev)
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mutex_unlock(&priv->lock);
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rtnl_unlock();
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if (!device_may_wakeup(priv->device) || !priv->plat->pmt) {
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rtnl_lock();
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phylink_start(priv->phylink);
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/* We may have called phylink_speed_down before */
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phylink_speed_up(priv->phylink);
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rtnl_unlock();
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}
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phylink_mac_change(priv->phylink, true);
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netif_device_attach(ndev);
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@ -170,6 +170,7 @@ struct plat_stmmacenet_data {
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int unicast_filter_entries;
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int tx_fifo_size;
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int rx_fifo_size;
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u32 addr64;
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u32 rx_queues_to_use;
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u32 tx_queues_to_use;
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u8 rx_sched_algorithm;
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