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drm/amd/display: set drr during program timing.

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Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun 2017-06-26 16:25:10 -04:00 committed by Alex Deucher
parent 7a8368e6f5
commit 97416d4cbb
3 changed files with 45 additions and 3 deletions
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21
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
View File

@ -629,6 +629,27 @@ void dce110_timing_generator_program_blanking(
CRTC_V_TOTAL);
dm_write_reg(ctx, addr, value);
/* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
* V_TOTAL_MIN are equal to V_TOTAL.
*/
addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
value = dm_read_reg(ctx, addr);
set_reg_field_value(
value,
timing->v_total - 1,
CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX);
dm_write_reg(ctx, addr, value);
addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
value = dm_read_reg(ctx, addr);
set_reg_field_value(
value,
timing->v_total - 1,
CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN);
dm_write_reg(ctx, addr, value);
addr = CRTC_REG(mmCRTC_H_BLANK_START_END);
value = dm_read_reg(ctx, addr);

19
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
View File

@ -441,15 +441,28 @@ void dce120_timing_generator_program_blanking(
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
CRTC_REG_UPDATE(
CRTC0_CRTC_H_TOTAL,
CRTC_H_TOTAL,
timing->h_total - 1);
CRTC0_CRTC_H_TOTAL,
CRTC_H_TOTAL,
timing->h_total - 1);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL,
CRTC_V_TOTAL,
timing->v_total - 1);
/* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
* V_TOTAL_MIN are equal to V_TOTAL.
*/
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX,
timing->v_total - 1);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN,
timing->v_total - 1);
tmp1 = timing->h_total -
(h_sync_start + timing->h_border_left);
tmp2 = tmp1 + timing->h_addressable +

8
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
View File

@ -177,6 +177,14 @@ static void tgn10_program_timing(
REG_SET(OTG_V_TOTAL, 0,
OTG_V_TOTAL, v_total);
/* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
* OTG_V_TOTAL_MIN are equal to V_TOTAL.
*/
REG_SET(OTG_V_TOTAL_MAX, 0,
OTG_V_TOTAL_MAX, v_total);
REG_SET(OTG_V_TOTAL_MIN, 0,
OTG_V_TOTAL_MIN, v_total);
/* v_sync_start = 0, v_sync_end = v_sync_width */
v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;