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MIPS: simplify CONFIG_DMA_NONCOHERENT ifdefs

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CONFIG_DMA_MAYBE_COHERENT already selects CONFIG_DMA_NONCOHERENT, so we
can remove the extra conditions.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19529/
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-mips@linux-mips.org
This commit is contained in:
Christoph Hellwig 2018-06-15 13:08:31 +02:00 committed by Paul Burton
parent 9c78ecaf7b
commit 972dc3b79f
No known key found for this signature in database
GPG Key ID: 3EA79FACB57500DD
3 changed files with 6 additions and 6 deletions
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4
arch/mips/include/asm/io.h
View File

@ -590,7 +590,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
* *
* This API used to be exported; it now is for arch code internal use only. * This API used to be exported; it now is for arch code internal use only.
*/ */
#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) #ifdef CONFIG_DMA_NONCOHERENT
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
@ -609,7 +609,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
#define dma_cache_inv(start,size) \ #define dma_cache_inv(start,size) \
do { (void) (start); (void) (size); } while (0) do { (void) (start); (void) (size); } while (0)
#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ #endif /* CONFIG_DMA_NONCOHERENT */
/* /*
* Read a 32-bit register that requires a 64-bit read cycle on the bus. * Read a 32-bit register that requires a 64-bit read cycle on the bus.

4
arch/mips/mm/c-r4k.c
View File

@ -830,7 +830,7 @@ static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
return __r4k_flush_icache_range(start, end, true); return __r4k_flush_icache_range(start, end, true);
} }
#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) #ifdef CONFIG_DMA_NONCOHERENT
static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{ {
@ -904,7 +904,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
bc_inv(addr, size); bc_inv(addr, size);
__sync(); __sync();
} }
#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ #endif /* CONFIG_DMA_NONCOHERENT */
struct flush_cache_sigtramp_args { struct flush_cache_sigtramp_args {
struct mm_struct *mm; struct mm_struct *mm;

4
arch/mips/mm/cache.c
View File

@ -56,7 +56,7 @@ EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
EXPORT_SYMBOL(flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page);
EXPORT_SYMBOL(flush_icache_all); EXPORT_SYMBOL(flush_icache_all);
#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) #ifdef CONFIG_DMA_NONCOHERENT
/* DMA cache operations. */ /* DMA cache operations. */
void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
@ -65,7 +65,7 @@ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
EXPORT_SYMBOL(_dma_cache_wback_inv); EXPORT_SYMBOL(_dma_cache_wback_inv);
#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ #endif /* CONFIG_DMA_NONCOHERENT */
/* /*
* We could optimize the case where the cache argument is not BCACHE but * We could optimize the case where the cache argument is not BCACHE but