forked from Minki/linux
ASoC: fix pxa-ssp compiling issue under mach-mmp
pxa-ssp.c uses API like cpu_is_pxa3xx(), cpu_is_pxa2xx(), which is defined under arch-pxa architecture, and drivers under mach-mmp can't find it. so just use ssp->type to replace that API. Signed-off-by: Qiao Zhou <zhouqiao@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Qiao Zhou
Mark Brown
parent
601722157b
commit
972a55b62d
@ -160,6 +160,7 @@ enum pxa_ssp_type {
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PXA25x_SSP, /* pxa 210, 250, 255, 26x */
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PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
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PXA27x_SSP,
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PXA3xx_SSP,
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PXA168_SSP,
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PXA910_SSP,
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CE4100_SSP,
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@ -33,7 +33,6 @@
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#include <mach/hardware.h>
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#include <mach/dma.h>
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#include <mach/audio.h>
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#include "../../arm/pxa2xx-pcm.h"
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#include "pxa-ssp.h"
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@ -194,7 +193,7 @@ static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
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{
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u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
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if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
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if (ssp->type == PXA25x_SSP) {
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sscr0 &= ~0x0000ff00;
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sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
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} else {
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@ -212,7 +211,7 @@ static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
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u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
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u32 div;
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if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
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if (ssp->type == PXA25x_SSP)
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div = ((sscr0 >> 8) & 0xff) * 2 + 2;
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else
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div = ((sscr0 >> 8) & 0xfff) + 1;
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@ -242,7 +241,7 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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break;
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case PXA_SSP_CLK_PLL:
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/* Internal PLL is fixed */
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if (cpu_is_pxa25x())
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if (ssp->type == PXA25x_SSP)
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priv->sysclk = 1843200;
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else
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priv->sysclk = 13000000;
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@ -266,11 +265,11 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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/* The SSP clock must be disabled when changing SSP clock mode
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* on PXA2xx. On PXA3xx it must be enabled when doing so. */
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if (!cpu_is_pxa3xx())
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if (ssp->type != PXA3xx_SSP)
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clk_disable(ssp->clk);
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val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
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pxa_ssp_write_reg(ssp, SSCR0, val);
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if (!cpu_is_pxa3xx())
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if (ssp->type != PXA3xx_SSP)
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clk_enable(ssp->clk);
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return 0;
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@ -294,24 +293,20 @@ static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
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case PXA_SSP_AUDIO_DIV_SCDB:
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val = pxa_ssp_read_reg(ssp, SSACD);
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val &= ~SSACD_SCDB;
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#if defined(CONFIG_PXA3xx)
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if (cpu_is_pxa3xx())
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if (ssp->type == PXA3xx_SSP)
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val &= ~SSACD_SCDX8;
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#endif
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switch (div) {
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case PXA_SSP_CLK_SCDB_1:
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val |= SSACD_SCDB;
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break;
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case PXA_SSP_CLK_SCDB_4:
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break;
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#if defined(CONFIG_PXA3xx)
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case PXA_SSP_CLK_SCDB_8:
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if (cpu_is_pxa3xx())
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if (ssp->type == PXA3xx_SSP)
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val |= SSACD_SCDX8;
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else
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return -EINVAL;
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break;
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#endif
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default:
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return -EINVAL;
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}
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@ -337,10 +332,8 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
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struct ssp_device *ssp = priv->ssp;
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u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
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#if defined(CONFIG_PXA3xx)
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if (cpu_is_pxa3xx())
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if (ssp->type == PXA3xx_SSP)
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pxa_ssp_write_reg(ssp, SSACDD, 0);
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#endif
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switch (freq_out) {
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case 5622000:
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@ -365,11 +358,10 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
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break;
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default:
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#ifdef CONFIG_PXA3xx
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/* PXA3xx has a clock ditherer which can be used to generate
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* a wider range of frequencies - calculate a value for it.
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*/
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if (cpu_is_pxa3xx()) {
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if (ssp->type == PXA3xx_SSP) {
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u32 val;
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u64 tmp = 19968;
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tmp *= 1000000;
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@ -386,7 +378,6 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
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val, freq_out);
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break;
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}
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#endif
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return -EINVAL;
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}
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@ -590,10 +581,8 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
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/* bit size */
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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#ifdef CONFIG_PXA3xx
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if (cpu_is_pxa3xx())
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if (ssp->type == PXA3xx_SSP)
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sscr0 |= SSCR0_FPCKE;
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#endif
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sscr0 |= SSCR0_DataSize(16);
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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@ -618,9 +607,7 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
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* trying and failing a lot; some of the registers
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* needed for that mode are only available on PXA3xx.
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*/
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#ifdef CONFIG_PXA3xx
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if (!cpu_is_pxa3xx())
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if (ssp->type != PXA3xx_SSP)
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return -EINVAL;
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sspsp |= SSPSP_SFRMWDTH(width * 2);
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@ -628,9 +615,6 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
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sspsp |= SSPSP_EDMYSTOP(3);
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sspsp |= SSPSP_DMYSTOP(3);
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sspsp |= SSPSP_DMYSTRT(1);
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#else
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return -EINVAL;
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#endif
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} else {
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/* The frame width is the width the LRCLK is
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* asserted for; the delay is expressed in
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