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sh: remove intc2 code

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There is no point in keeping around the now unused intc2 code.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm 2007-08-03 14:29:20 +09:00 committed by Paul Mundt
parent 48180cab3a
commit 96290d808f
5 changed files with 0 additions and 109 deletions
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3
arch/sh/Kconfig
View File

@ -181,9 +181,6 @@ config CPU_HAS_MASKREG_IRQ
config CPU_HAS_INTC_IRQ config CPU_HAS_INTC_IRQ
bool bool
config CPU_HAS_INTC2_IRQ
bool
config CPU_HAS_IPR_IRQ config CPU_HAS_IPR_IRQ
bool bool

1
arch/sh/kernel/cpu/irq/Makefile
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@ -6,4 +6,3 @@ obj-y += imask.o
obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o
obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o

86
arch/sh/kernel/cpu/irq/intc2.c
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@ -1,86 +0,0 @@
/*
* Interrupt handling for INTC2-based IRQ.
*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
* Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* These are the "new Hitachi style" interrupts, as present on the
* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/smp.h>
static inline struct intc2_desc *get_intc2_desc(unsigned int irq)
{
struct irq_chip *chip = get_irq_chip(irq);
return (void *)((char *)chip - offsetof(struct intc2_desc, chip));
}
static void disable_intc2_irq(unsigned int irq)
{
struct intc2_data *p = get_irq_chip_data(irq);
struct intc2_desc *d = get_intc2_desc(irq);
ctrl_outl(1 << p->msk_shift, d->msk_base + p->msk_offset +
(hard_smp_processor_id() * 4));
}
static void enable_intc2_irq(unsigned int irq)
{
struct intc2_data *p = get_irq_chip_data(irq);
struct intc2_desc *d = get_intc2_desc(irq);
ctrl_outl(1 << p->msk_shift, d->mskclr_base + p->msk_offset +
(hard_smp_processor_id() * 4));
}
/*
* Setup an INTC2 style interrupt.
* NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
* allowing the use of the numbers straight out of the datasheet.
* For example:
* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
* would be: ^ ^ ^ ^
* | | | |
* { 84, 0, 16, 0, 13 },
*
* in the intc2_data table.
*/
void register_intc2_controller(struct intc2_desc *desc)
{
int i;
desc->chip.mask = disable_intc2_irq;
desc->chip.unmask = enable_intc2_irq;
desc->chip.mask_ack = disable_intc2_irq;
for (i = 0; i < desc->nr_irqs; i++) {
unsigned long ipr, flags;
struct intc2_data *p = desc->intc2_data + i;
disable_irq_nosync(p->irq);
if (desc->prio_base) {
/* Set the priority level */
local_irq_save(flags);
ipr = ctrl_inl(desc->prio_base + p->ipr_offset);
ipr &= ~(0xf << p->ipr_shift);
ipr |= p->priority << p->ipr_shift;
ctrl_outl(ipr, desc->prio_base + p->ipr_offset);
local_irq_restore(flags);
}
set_irq_chip_and_handler_name(p->irq, &desc->chip,
handle_level_irq, "level");
set_irq_chip_data(p->irq, p);
disable_intc2_irq(p->irq);
}
}

1
arch/sh/mm/Kconfig
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@ -31,7 +31,6 @@ config CPU_SH4AL_DSP
config CPU_SUBTYPE_ST40 config CPU_SUBTYPE_ST40
bool bool
select CPU_SH4 select CPU_SH4
select CPU_HAS_INTC2_IRQ
config CPU_SHX2 config CPU_SHX2
bool bool

18
include/asm-sh/hw_irq.h
View File

@ -6,24 +6,6 @@
extern atomic_t irq_err_count; extern atomic_t irq_err_count;
struct intc2_data {
unsigned short irq;
unsigned char ipr_offset, ipr_shift;
unsigned char msk_offset, msk_shift;
unsigned char priority;
};
struct intc2_desc {
unsigned long prio_base;
unsigned long msk_base;
unsigned long mskclr_base;
struct intc2_data *intc2_data;
unsigned int nr_irqs;
struct irq_chip chip;
};
void register_intc2_controller(struct intc2_desc *);
struct ipr_data { struct ipr_data {
unsigned char irq; unsigned char irq;
unsigned char ipr_idx; /* Index for the IPR registered */ unsigned char ipr_idx; /* Index for the IPR registered */