forked from Minki/linux
i40e/i40evf: bundle more descriptors when allocating buffers
Double the number of descriptors we'll bundle into one tail bump when receiving. Empirical testing has shown that we reduce CPU utilization and don't appear to reduce throughput or packet rate. 32 seems to be the sweet spot, as it's half the default polling budget, so we'd essentially reduce from 4 tail writes when polling down to 2. Increasing this up to 64 appears to have negative impacts as it may become possible that we don't bump the tail each time we get polled, which could cause a long delay between returning descriptors to the hardware. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
11f29003d6
commit
95bc2fb4c6
@ -208,7 +208,7 @@ static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc,
|
||||
}
|
||||
|
||||
/* How many Rx Buffers do we bundle into one write to the hardware ? */
|
||||
#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
||||
#define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */
|
||||
#define I40E_RX_INCREMENT(r, i) \
|
||||
do { \
|
||||
(i)++; \
|
||||
|
@ -191,7 +191,7 @@ static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc,
|
||||
}
|
||||
|
||||
/* How many Rx Buffers do we bundle into one write to the hardware ? */
|
||||
#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
||||
#define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */
|
||||
#define I40E_RX_INCREMENT(r, i) \
|
||||
do { \
|
||||
(i)++; \
|
||||
|
Loading…
Reference in New Issue
Block a user