forked from Minki/linux
ARM: dts: fix omap3 dss clock handle names
The DSS fclk and iclk handles are named differently on OMAP3430 ES1 than on later OMAP revisions. The ES1 has handles 'dss1_alwon_fck_3430es1' and 'dss_ick_3430es1', whereas later revisions have similar names but ending with 'es2'. This means we don't have one clock handle to which we could refer to when defining the DSS clocks. However, as the namespaces are separate for ES1 and ES2+ OMAPs, we can just rename the handles to 'dss1_alwon_fck' and 'dss_ick' for both ES1 and ES2+, removing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Tested-by: Marek Belisko <marek@goldelico.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
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@ -152,7 +152,7 @@
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clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
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};
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dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
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dss1_alwon_fck: dss1_alwon_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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@ -161,7 +161,7 @@
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ti,set-rate-parent;
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};
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dss_ick_3430es1: dss_ick_3430es1 {
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dss_ick: dss_ick_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&l4_ick>;
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@ -184,7 +184,7 @@
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
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<&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
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<&dss1_alwon_fck>, <&dss_ick>;
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};
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d2d_clkdm: d2d_clkdm {
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@ -160,7 +160,7 @@
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ti,bit-shift = <30>;
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};
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dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
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dss1_alwon_fck: dss1_alwon_fck_3430es2 {
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#clock-cells = <0>;
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compatible = "ti,dss-gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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@ -169,7 +169,7 @@
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ti,set-rate-parent;
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};
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dss_ick_3430es2: dss_ick_3430es2 {
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dss_ick: dss_ick_3430es2 {
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#clock-cells = <0>;
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compatible = "ti,omap3-dss-interface-clock";
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clocks = <&l4_ick>;
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@ -216,7 +216,7 @@
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
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<&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
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<&dss1_alwon_fck>, <&dss_ick>;
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};
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core_l4_clkdm: core_l4_clkdm {
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